Commit 492061bf authored Apr 22, 2023 by Krzysztof Kozlowski Committed by Matthias Brugger May 29, 2023

arm64: dts: mediatek: add missing cache properties

As all level 2 and level 3 caches are unified, add required
cache-unified properties to fix warnings like:

mt7622-rfb1.dtb: l2-cache: 'cache-unified' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20230421223157.115367-1-krzysztof.kozlowski@linaro.org

Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>

parent ea6c5f21

arch/arm64/boot/dts/mediatek/mt7622.dtsi

+1 −0

Original line number	Diff line number	Diff line
		@@ -101,6 +101,7 @@ cpu1: cpu@1 {
		L2: l2-cache {
		compatible = "cache";
		cache-level = <2>;
		cache-unified;
		};
		};

arch/arm64/boot/dts/mediatek/mt8186.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -258,6 +258,7 @@ l2_0: l2-cache0 {
		cache-line-size = <64>;
		cache-sets = <512>;
		next-level-cache = <&l3_0>;
		cache-unified;
		};

		l2_1: l2-cache1 {
		@@ -267,6 +268,7 @@ l2_1: l2-cache1 {
		cache-line-size = <64>;
		cache-sets = <512>;
		next-level-cache = <&l3_0>;
		cache-unified;
		};

		l3_0: l3-cache {

arch/arm64/boot/dts/mediatek/mt8192.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -228,6 +228,7 @@ l2_0: l2-cache0 {
		cache-line-size = <64>;
		cache-sets = <512>;
		next-level-cache = <&l3_0>;
		cache-unified;
		};

		l2_1: l2-cache1 {
		@@ -237,6 +238,7 @@ l2_1: l2-cache1 {
		cache-line-size = <64>;
		cache-sets = <512>;
		next-level-cache = <&l3_0>;
		cache-unified;
		};

		l3_0: l3-cache {

arch/arm64/boot/dts/mediatek/mt8195.dtsi

+2 −0

Original line number	Diff line number	Diff line
		@@ -285,6 +285,7 @@ l2_0: l2-cache0 {
		cache-line-size = <64>;
		cache-sets = <512>;
		next-level-cache = <&l3_0>;
		cache-unified;
		};

		l2_1: l2-cache1 {
		@@ -294,6 +295,7 @@ l2_1: l2-cache1 {
		cache-line-size = <64>;
		cache-sets = <512>;
		next-level-cache = <&l3_0>;
		cache-unified;
		};

		l3_0: l3-cache {