Loading arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +1 −1 Original line number Diff line number Diff line Loading @@ -100,7 +100,7 @@ typedef volatile struct au1xxx_ddma_desc { u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ /* * First 32 bytes are HW specific!!! * Lets have some SW data following -- make sure it's 32 bytes. * Let's have some SW data following -- make sure it's 32 bytes. */ u32 sw_status; u32 sw_context; Loading arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +1 −1 Original line number Diff line number Diff line Loading @@ -22,7 +22,7 @@ /* * during early_printk no ioremap possible at this early stage * lets use KSEG1 instead * let's use KSEG1 instead */ #define LTQ_ASC0_BASE_ADDR 0x1E100C00 #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) Loading arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +1 −1 Original line number Diff line number Diff line Loading @@ -75,7 +75,7 @@ extern __iomem void *ltq_cgu_membase; /* * during early_printk no ioremap is possible * lets use KSEG1 instead * let's use KSEG1 instead */ #define LTQ_ASC1_BASE_ADDR 0x1E100C00 #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) Loading arch/mips/kernel/branch.c +2 −2 Original line number Diff line number Diff line Loading @@ -481,7 +481,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, /* * OK we are here either because we hit a NAL * instruction or because we are emulating an * old bltzal{,l} one. Lets figure out what the * old bltzal{,l} one. Let's figure out what the * case really is. */ if (!insn.i_format.rs) { Loading Loading @@ -515,7 +515,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, /* * OK we are here either because we hit a BAL * instruction or because we are emulating an * old bgezal{,l} one. Lets figure out what the * old bgezal{,l} one. Let's figure out what the * case really is. */ if (!insn.i_format.rs) { Loading arch/mips/kernel/elf.c +1 −1 Original line number Diff line number Diff line Loading @@ -88,7 +88,7 @@ int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf, elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32; flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags; /* Lets see if this is an O32 ELF */ /* Let's see if this is an O32 ELF */ if (elf32) { if (flags & EF_MIPS_FP64) { /* Loading Loading
arch/mips/include/asm/mach-au1x00/au1xxx_dbdma.h +1 −1 Original line number Diff line number Diff line Loading @@ -100,7 +100,7 @@ typedef volatile struct au1xxx_ddma_desc { u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ /* * First 32 bytes are HW specific!!! * Lets have some SW data following -- make sure it's 32 bytes. * Let's have some SW data following -- make sure it's 32 bytes. */ u32 sw_status; u32 sw_context; Loading
arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +1 −1 Original line number Diff line number Diff line Loading @@ -22,7 +22,7 @@ /* * during early_printk no ioremap possible at this early stage * lets use KSEG1 instead * let's use KSEG1 instead */ #define LTQ_ASC0_BASE_ADDR 0x1E100C00 #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) Loading
arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +1 −1 Original line number Diff line number Diff line Loading @@ -75,7 +75,7 @@ extern __iomem void *ltq_cgu_membase; /* * during early_printk no ioremap is possible * lets use KSEG1 instead * let's use KSEG1 instead */ #define LTQ_ASC1_BASE_ADDR 0x1E100C00 #define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) Loading
arch/mips/kernel/branch.c +2 −2 Original line number Diff line number Diff line Loading @@ -481,7 +481,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, /* * OK we are here either because we hit a NAL * instruction or because we are emulating an * old bltzal{,l} one. Lets figure out what the * old bltzal{,l} one. Let's figure out what the * case really is. */ if (!insn.i_format.rs) { Loading Loading @@ -515,7 +515,7 @@ int __compute_return_epc_for_insn(struct pt_regs *regs, /* * OK we are here either because we hit a BAL * instruction or because we are emulating an * old bgezal{,l} one. Lets figure out what the * old bgezal{,l} one. Let's figure out what the * case really is. */ if (!insn.i_format.rs) { Loading
arch/mips/kernel/elf.c +1 −1 Original line number Diff line number Diff line Loading @@ -88,7 +88,7 @@ int arch_elf_pt_proc(void *_ehdr, void *_phdr, struct file *elf, elf32 = ehdr->e32.e_ident[EI_CLASS] == ELFCLASS32; flags = elf32 ? ehdr->e32.e_flags : ehdr->e64.e_flags; /* Lets see if this is an O32 ELF */ /* Let's see if this is an O32 ELF */ if (elf32) { if (flags & EF_MIPS_FP64) { /* Loading