Unverified Commit 49625c6e authored by Haylen Chu's avatar Haylen Chu Committed by Yixun Lan
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clk: spacemit: k1: Add TWSI8 bus and function clocks 



The control register for TWSI8 clocks, APBC_TWSI8_CLK_RST, contains mux
selection bits, reset assertion bit and enable bits for function and bus
clocks. It has a quirk that reading always results in zero.

As a workaround, let's hardcode the mux value as zero to select
pll1_d78_31p5 as parent and treat twsi8_clk as a gate, whose enable mask
is combined from the real bus and function clocks to avoid the
write-only register being shared between two clk_hws, in which case
updates of one clk_hw zero the other's bits.

With a 1:1 factor serving as placeholder for the bus clock, the I2C-8
controller could be brought up, which is essential for boards attaching
power-management chips to it.

Signed-off-by: default avatarHaylen Chu <heylenay@4d2.org>
Reviewed-by: default avatarAlex Elder <elder@riscstar.com>
Reviewed-by: default avatarYixun Lan <dlan@gentoo.org>
Link: https://lore.kernel.org/r/20250416135406.16284-5-heylenay@4d2.org


Signed-off-by: default avatarYixun Lan <dlan@gentoo.org>
parent 1b72c59d

drivers/clk/spacemit/ccu-k1.c

+10 −0
Original line number Diff line number Diff line
@@ -328,6 +328,12 @@ CCU_MUX_GATE_DEFINE(twsi4_clk, twsi_parents, APBC_TWSI4_CLK_RST, 4, 3, BIT(1), 0 
CCU_MUX_GATE_DEFINE(twsi5_clk, twsi_parents, APBC_TWSI5_CLK_RST, 4, 3, BIT(1), 0);

CCU_MUX_GATE_DEFINE(twsi6_clk, twsi_parents, APBC_TWSI6_CLK_RST, 4, 3, BIT(1), 0);

CCU_MUX_GATE_DEFINE(twsi7_clk, twsi_parents, APBC_TWSI7_CLK_RST, 4, 3, BIT(1), 0);

/*

 * APBC_TWSI8_CLK_RST has a quirk that reading always results in zero.

 * Combine functional and bus bits together as a gate to avoid sharing the

 * write-only register between different clock hardwares.

 */

CCU_GATE_DEFINE(twsi8_clk, CCU_PARENT_HW(pll1_d78_31p5), APBC_TWSI8_CLK_RST, BIT(1) | BIT(0), 0);



static const struct clk_parent_data timer_parents[] = {

	CCU_PARENT_HW(pll1_d192_12p8),
@@ -412,6 +418,8 @@ CCU_GATE_DEFINE(twsi4_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI4_CLK_RST, BIT(0 
CCU_GATE_DEFINE(twsi5_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI5_CLK_RST, BIT(0), 0);

CCU_GATE_DEFINE(twsi6_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI6_CLK_RST, BIT(0), 0);

CCU_GATE_DEFINE(twsi7_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TWSI7_CLK_RST, BIT(0), 0);

/* Placeholder to workaround quirk of the register */

CCU_FACTOR_DEFINE(twsi8_bus_clk, CCU_PARENT_HW(apb_clk), 1, 1);



CCU_GATE_DEFINE(timers1_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS1_CLK_RST, BIT(0), 0);

CCU_GATE_DEFINE(timers2_bus_clk, CCU_PARENT_HW(apb_clk), APBC_TIMERS2_CLK_RST, BIT(0), 0);
@@ -896,6 +904,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { 
	[CLK_TWSI5]		= &twsi5_clk.common.hw,

	[CLK_TWSI6]		= &twsi6_clk.common.hw,

	[CLK_TWSI7]		= &twsi7_clk.common.hw,

	[CLK_TWSI8]		= &twsi8_clk.common.hw,

	[CLK_TIMERS1]		= &timers1_clk.common.hw,

	[CLK_TIMERS2]		= &timers2_clk.common.hw,

	[CLK_AIB]		= &aib_clk.common.hw,
@@ -947,6 +956,7 @@ static struct clk_hw *k1_ccu_apbc_hws[] = { 
	[CLK_TWSI5_BUS]		= &twsi5_bus_clk.common.hw,

	[CLK_TWSI6_BUS]		= &twsi6_bus_clk.common.hw,

	[CLK_TWSI7_BUS]		= &twsi7_bus_clk.common.hw,

	[CLK_TWSI8_BUS]		= &twsi8_bus_clk.common.hw,

	[CLK_TIMERS1_BUS]	= &timers1_bus_clk.common.hw,

	[CLK_TIMERS2_BUS]	= &timers2_bus_clk.common.hw,

	[CLK_AIB_BUS]		= &aib_bus_clk.common.hw,