Commit 49ed320d authored by Tiezhu Yang's avatar Tiezhu Yang Committed by Huacai Chen
Browse files

LoongArch: Add larch_insn_gen_break() to generate break insns 



There exist various break insns such as BRK_KPROBE_BP, BRK_KPROBE_SSTEPBP,
BRK_UPROBE_BP and BRK_UPROBE_XOLBP, add larch_insn_gen_break() to generate
break insns simpler, this is preparation for later patch.

Tested-by: default avatarJeff Xie <xiehuan09@gmail.com>
Signed-off-by: default avatarTiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: default avatarHuacai Chen <chenhuacai@loongson.cn>
parent b82fad4d

arch/loongarch/include/asm/inst.h

+12 −0
Original line number Diff line number Diff line
@@ -482,6 +482,8 @@ u32 larch_insn_gen_nop(void); 
u32 larch_insn_gen_b(unsigned long pc, unsigned long dest);

u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest);



u32 larch_insn_gen_break(int imm);



u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk);

u32 larch_insn_gen_move(enum loongarch_gpr rd, enum loongarch_gpr rj);
@@ -500,6 +502,16 @@ static inline bool unsigned_imm_check(unsigned long val, unsigned int bit) 
	return val < (1UL << bit);

}



#define DEF_EMIT_REG0I15_FORMAT(NAME, OP)				\

static inline void emit_##NAME(union loongarch_instruction *insn,	\

			       int imm)					\

{									\

	insn->reg0i15_format.opcode = OP;				\

	insn->reg0i15_format.immediate = imm;				\

}



DEF_EMIT_REG0I15_FORMAT(break, break_op)



#define DEF_EMIT_REG0I26_FORMAT(NAME, OP)				\

static inline void emit_##NAME(union loongarch_instruction *insn,	\

			       int offset)				\

arch/loongarch/kernel/inst.c

+14 −0
Original line number Diff line number Diff line
@@ -253,6 +253,20 @@ u32 larch_insn_gen_bl(unsigned long pc, unsigned long dest) 
	return insn.word;

}



u32 larch_insn_gen_break(int imm)

{

	union loongarch_instruction insn;



	if (imm < 0 || imm >= SZ_32K) {

		pr_warn("The generated break instruction is out of range.\n");

		return INSN_BREAK;

	}



	emit_break(&insn, imm);



	return insn.word;

}



u32 larch_insn_gen_or(enum loongarch_gpr rd, enum loongarch_gpr rj, enum loongarch_gpr rk)

{

	union loongarch_instruction insn;