Commit 49f26218 authored by Dmytro Laktyushkin's avatar Dmytro Laktyushkin Committed by Alex Deucher
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drm/amd/display: fix dcn315 single stream crb allocation 



Change to improve avoiding asymetric crb calculations for single stream
scenarios.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Acked-by: default avatarStylon Wang <stylon.wang@amd.com>
Signed-off-by: default avatarDmytro Laktyushkin <dmytro.laktyushkin@amd.com>
Reviewed-by: default avatarCharlene Liu <Charlene.Liu@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 869bcf59

drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c

+12 −3
Original line number Diff line number Diff line
@@ -1628,6 +1628,10 @@ static bool allow_pixel_rate_crb(struct dc *dc, struct dc_state *context) 
	int i;

	struct resource_context *res_ctx = &context->res_ctx;



	/*Don't apply for single stream*/

	if (context->stream_count < 2)

		return false;



	for (i = 0; i < dc->res_pool->pipe_count; i++) {

		if (!res_ctx->pipe_ctx[i].stream)

			continue;
@@ -1727,19 +1731,23 @@ static int dcn315_populate_dml_pipes_from_context( 
		pipe_cnt++;

	}



	/* Spread remaining unreserved crb evenly among all pipes, use default policy if not enough det or single pipe */

	/* Spread remaining unreserved crb evenly among all pipes*/

	if (pixel_rate_crb) {

		for (i = 0, pipe_cnt = 0, crb_idx = 0; i < dc->res_pool->pipe_count; i++) {

			pipe = &res_ctx->pipe_ctx[i];

			if (!pipe->stream)

				continue;



			/* Do not use asymetric crb if not enough for pstate support */

			if (remaining_det_segs < 0) {

				pipes[pipe_cnt].pipe.src.det_size_override = 0;

				continue;

			}



			if (!pipe->top_pipe && !pipe->prev_odm_pipe) {

				bool split_required = pipe->stream->timing.pix_clk_100hz >= dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)

						|| (pipe->plane_state && pipe->plane_state->src_rect.width > 5120);



				if (remaining_det_segs < 0 || crb_pipes == 1)

					pipes[pipe_cnt].pipe.src.det_size_override = 0;

				if (remaining_det_segs > MIN_RESERVED_DET_SEGS)

					pipes[pipe_cnt].pipe.src.det_size_override += (remaining_det_segs - MIN_RESERVED_DET_SEGS) / crb_pipes +

							(crb_idx < (remaining_det_segs - MIN_RESERVED_DET_SEGS) % crb_pipes ? 1 : 0);
@@ -1755,6 +1763,7 @@ static int dcn315_populate_dml_pipes_from_context( 
				}

				/* Convert segments into size for DML use */

				pipes[pipe_cnt].pipe.src.det_size_override *= DCN3_15_CRB_SEGMENT_SIZE_KB;



				crb_idx++;

			}

			pipe_cnt++;