Commit 4a1574ce authored by Danila Tikhonov's avatar Danila Tikhonov Committed by Georgi Djakov
Browse files

interconnect: qcom: Add SM7150 driver support 



Add a driver that handles the different NoCs found on SM7150, based on the
downstream dtb.

Signed-off-by: default avatarDanila Tikhonov <danila@jiaxyga.com>
Link: https://lore.kernel.org/r/20240222174250.80493-3-danila@jiaxyga.com


Signed-off-by: default avatarGeorgi Djakov <djakov@kernel.org>
parent 9c405849

drivers/interconnect/qcom/Kconfig

+9 −0
Original line number Diff line number Diff line
@@ -209,6 +209,15 @@ config INTERCONNECT_QCOM_SM6350 
	  This is a driver for the Qualcomm Network-on-Chip on sm6350-based

	  platforms.



config INTERCONNECT_QCOM_SM7150

	tristate "Qualcomm SM7150 interconnect driver"

	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

	select INTERCONNECT_QCOM_RPMH

	select INTERCONNECT_QCOM_BCM_VOTER

	help

	  This is a driver for the Qualcomm Network-on-Chip on sm7150-based

	  platforms.



config INTERCONNECT_QCOM_SM8150

	tristate "Qualcomm SM8150 interconnect driver"

	depends on INTERCONNECT_QCOM_RPMH_POSSIBLE

drivers/interconnect/qcom/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -26,6 +26,7 @@ qnoc-sdx65-objs := sdx65.o 
qnoc-sdx75-objs				:= sdx75.o

qnoc-sm6115-objs			:= sm6115.o

qnoc-sm6350-objs			:= sm6350.o

qnoc-sm7150-objs			:= sm7150.o

qnoc-sm8150-objs			:= sm8150.o

qnoc-sm8250-objs			:= sm8250.o

qnoc-sm8350-objs			:= sm8350.o
@@ -58,6 +59,7 @@ obj-$(CONFIG_INTERCONNECT_QCOM_SDX65) += qnoc-sdx65.o 
obj-$(CONFIG_INTERCONNECT_QCOM_SDX75) += qnoc-sdx75.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM6115) += qnoc-sm6115.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM6350) += qnoc-sm6350.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM7150) += qnoc-sm7150.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM8150) += qnoc-sm8150.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM8250) += qnoc-sm8250.o

obj-$(CONFIG_INTERCONNECT_QCOM_SM8350) += qnoc-sm8350.o

drivers/interconnect/qcom/sm7150.c

0 → 100644
+1754 −0

File added.

Preview size limit exceeded, changes collapsed.

drivers/interconnect/qcom/sm7150.h

0 → 100644
+140 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Qualcomm #define SM7150 interconnect IDs

 *

 * Copyright (c) 2020, The Linux Foundation. All rights reserved.

 * Copyright (c) 2024, Danila Tikhonov <danila@jiaxyga.com>

 */



#ifndef __DRIVERS_INTERCONNECT_QCOM_SM7150_H

#define __DRIVERS_INTERCONNECT_QCOM_SM7150_H



#define SM7150_A1NOC_SNOC_MAS			0

#define SM7150_A1NOC_SNOC_SLV			1

#define SM7150_A2NOC_SNOC_MAS			2

#define SM7150_A2NOC_SNOC_SLV			3

#define SM7150_MASTER_A1NOC_CFG			4

#define SM7150_MASTER_A2NOC_CFG			5

#define SM7150_MASTER_AMPSS_M0			6

#define SM7150_MASTER_CAMNOC_HF0		7

#define SM7150_MASTER_CAMNOC_HF0_UNCOMP		8

#define SM7150_MASTER_CAMNOC_NRT		9

#define SM7150_MASTER_CAMNOC_NRT_UNCOMP		10

#define SM7150_MASTER_CAMNOC_RT			11

#define SM7150_MASTER_CAMNOC_RT_UNCOMP		12

#define SM7150_MASTER_CAMNOC_SF			13

#define SM7150_MASTER_CAMNOC_SF_UNCOMP		14

#define SM7150_MASTER_CNOC_A2NOC		15

#define SM7150_MASTER_CNOC_DC_NOC		16

#define SM7150_MASTER_CNOC_MNOC_CFG		17

#define SM7150_MASTER_COMPUTE_NOC		18

#define SM7150_MASTER_CRYPTO_CORE_0		19

#define SM7150_MASTER_EMMC			20

#define SM7150_MASTER_GEM_NOC_CFG		21

#define SM7150_MASTER_GEM_NOC_PCIE_SNOC		22

#define SM7150_MASTER_GEM_NOC_SNOC		23

#define SM7150_MASTER_GIC			24

#define SM7150_MASTER_GRAPHICS_3D		25

#define SM7150_MASTER_IPA			26

#define SM7150_MASTER_LLCC			27

#define SM7150_MASTER_MDP_PORT0			28

#define SM7150_MASTER_MDP_PORT1			29

#define SM7150_MASTER_MNOC_HF_MEM_NOC		30

#define SM7150_MASTER_MNOC_SF_MEM_NOC		31

#define SM7150_MASTER_NPU			32

#define SM7150_MASTER_PCIE			33

#define SM7150_MASTER_PIMEM			34

#define SM7150_MASTER_QDSS_BAM			35

#define SM7150_MASTER_QDSS_DAP			36

#define SM7150_MASTER_QDSS_ETR			37

#define SM7150_MASTER_QUP_0			38

#define SM7150_MASTER_QUP_1			39

#define SM7150_MASTER_ROTATOR			40

#define SM7150_MASTER_SDCC_2			41

#define SM7150_MASTER_SDCC_4			42

#define SM7150_MASTER_SNOC_CFG			43

#define SM7150_MASTER_SNOC_GC_MEM_NOC		44

#define SM7150_MASTER_SNOC_SF_MEM_NOC		45

#define SM7150_MASTER_SPDM			46

#define SM7150_MASTER_SYS_TCU			47

#define SM7150_MASTER_TSIF			48

#define SM7150_MASTER_UFS_MEM			49

#define SM7150_MASTER_USB3			50

#define SM7150_MASTER_VIDEO_P0			51

#define SM7150_MASTER_VIDEO_P1			52

#define SM7150_MASTER_VIDEO_PROC		53

#define SM7150_SLAVE_A1NOC_CFG			54

#define SM7150_SLAVE_A2NOC_CFG			55

#define SM7150_SLAVE_AHB2PHY_NORTH		56

#define SM7150_SLAVE_AHB2PHY_SOUTH		57

#define SM7150_SLAVE_AHB2PHY_WEST		58

#define SM7150_SLAVE_ANOC_PCIE_GEM_NOC		59

#define SM7150_SLAVE_AOP			60

#define SM7150_SLAVE_AOSS			61

#define SM7150_SLAVE_APPSS			62

#define SM7150_SLAVE_CAMERA_CFG			63

#define SM7150_SLAVE_CAMERA_NRT_THROTTLE_CFG	64

#define SM7150_SLAVE_CAMERA_RT_THROTTLE_CFG	65

#define SM7150_SLAVE_CAMNOC_UNCOMP		66

#define SM7150_SLAVE_CDSP_CFG			67

#define SM7150_SLAVE_CDSP_GEM_NOC		68

#define SM7150_SLAVE_CLK_CTL			69

#define SM7150_SLAVE_CNOC_A2NOC			70

#define SM7150_SLAVE_CNOC_DDRSS			71

#define SM7150_SLAVE_CNOC_MNOC_CFG		72

#define SM7150_SLAVE_CRYPTO_0_CFG		73

#define SM7150_SLAVE_DISPLAY_CFG		74

#define SM7150_SLAVE_DISPLAY_THROTTLE_CFG	75

#define SM7150_SLAVE_EBI_CH0			76

#define SM7150_SLAVE_EMMC_CFG			77

#define SM7150_SLAVE_GEM_NOC_CFG		78

#define SM7150_SLAVE_GEM_NOC_SNOC		79

#define SM7150_SLAVE_GLM			80

#define SM7150_SLAVE_GRAPHICS_3D_CFG		81

#define SM7150_SLAVE_IMEM_CFG			82

#define SM7150_SLAVE_IPA_CFG			83

#define SM7150_SLAVE_LLCC			84

#define SM7150_SLAVE_LLCC_CFG			85

#define SM7150_SLAVE_MNOC_HF_MEM_NOC		86

#define SM7150_SLAVE_MNOC_SF_MEM_NOC		87

#define SM7150_SLAVE_MSS_PROC_MS_MPU_CFG	88

#define SM7150_SLAVE_OCIMEM			89

#define SM7150_SLAVE_PCIE_CFG			90

#define SM7150_SLAVE_PDM			91

#define SM7150_SLAVE_PIMEM			92

#define SM7150_SLAVE_PIMEM_CFG			93

#define SM7150_SLAVE_PRNG			94

#define SM7150_SLAVE_QDSS_CFG			95

#define SM7150_SLAVE_QDSS_STM			96

#define SM7150_SLAVE_QUP_0			97

#define SM7150_SLAVE_QUP_1			98

#define SM7150_SLAVE_RBCPR_CX_CFG		99

#define SM7150_SLAVE_RBCPR_MX_CFG		100

#define SM7150_SLAVE_SDCC_2			101

#define SM7150_SLAVE_SDCC_4			102

#define SM7150_SLAVE_SERVICE_A1NOC		103

#define SM7150_SLAVE_SERVICE_A2NOC		104

#define SM7150_SLAVE_SERVICE_CNOC		105

#define SM7150_SLAVE_SERVICE_GEM_NOC		106

#define SM7150_SLAVE_SERVICE_MNOC		107

#define SM7150_SLAVE_SERVICE_SNOC		108

#define SM7150_SLAVE_SNOC_CFG			109

#define SM7150_SLAVE_SNOC_GEM_NOC_GC		110

#define SM7150_SLAVE_SNOC_GEM_NOC_SF		111

#define SM7150_SLAVE_SPDM_WRAPPER		112

#define SM7150_SLAVE_TCSR			113

#define SM7150_SLAVE_TCU			114

#define SM7150_SLAVE_TLMM_NORTH			115

#define SM7150_SLAVE_TLMM_SOUTH			116

#define SM7150_SLAVE_TLMM_WEST			117

#define SM7150_SLAVE_TSIF			118

#define SM7150_SLAVE_UFS_MEM_CFG		119

#define SM7150_SLAVE_USB3			120

#define SM7150_SLAVE_VENUS_CFG			121

#define SM7150_SLAVE_VENUS_CVP_THROTTLE_CFG	122

#define SM7150_SLAVE_VENUS_THROTTLE_CFG		123

#define SM7150_SLAVE_VSENSE_CTRL_CFG		124

#define SM7150_SNOC_CNOC_MAS			125

#define SM7150_SNOC_CNOC_SLV			126



#endif