Commit 4a3e37b3 authored by Jiaxun Yang's avatar Jiaxun Yang Committed by Thomas Bogendoerfer
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MIPS: mipsmtregs: Fix target register for MFTC0 



Target register of mftc0 should be __res instead of $1, this is
a leftover from old .insn code.

Fixes: dd6d29a6 ("MIPS: Implement microMIPS MT ASE helpers")
Cc: stable@vger.kernel.org
Signed-off-by: default avatarJiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: default avatarThomas Bogendoerfer <tsbogend@alpha.franken.de>
parent 6e5aee08

arch/mips/include/asm/mipsmtregs.h

+1 −1
Original line number Diff line number Diff line
@@ -322,7 +322,7 @@ static inline void ehb(void) 
	"	.set	push				\n"	\

	"	.set	"MIPS_ISA_LEVEL"		\n"	\

	_ASM_SET_MFTC0							\

	"	mftc0	$1, " #rt ", " #sel "		\n"	\

	"	mftc0	%0, " #rt ", " #sel "		\n"	\

	_ASM_UNSET_MFTC0						\

	"	.set	pop				\n"	\

	: "=r" (__res));						\