Commit 4a8f8340 authored by Jett.Zhou's avatar Jett.Zhou Committed by Haojian Zhuang
Browse files

ARM: sa1100: clean up clock support 



Add rtc clock support and clean clock support for gpio.

Signed-off-by: default avatarJett.Zhou <jtzhou@marvell.com>
signed-off-by: default avatarHaojian Zhuang <haojian.zhuang@marvell.com>
parent 3888c090

arch/arm/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -754,7 +754,7 @@ config ARCH_SA1100 
	select ARCH_HAS_CPUFREQ

	select CPU_FREQ

	select GENERIC_CLOCKEVENTS

	select HAVE_CLK

	select CLKDEV_LOOKUP

	select HAVE_SCHED_CLOCK

	select TICK_ONESHOT

	select ARCH_REQUIRE_GPIOLIB

arch/arm/mach-sa1100/clock.c

+47 −35
Original line number Diff line number Diff line
@@ -11,17 +11,29 @@ 
#include <linux/clk.h>

#include <linux/spinlock.h>

#include <linux/mutex.h>

#include <linux/io.h>

#include <linux/clkdev.h>



#include <mach/hardware.h>



/*

 * Very simple clock implementation - we only have one clock to deal with.

 */

struct clkops {

	void			(*enable)(struct clk *);

	void			(*disable)(struct clk *);

};



struct clk {

	const struct clkops	*ops;

	unsigned int		enabled;

};



static void clk_gpio27_enable(void)

#define DEFINE_CLK(_name, _ops)				\

struct clk clk_##_name = {				\

		.ops	= _ops,				\

	}



static DEFINE_SPINLOCK(clocks_lock);



static void clk_gpio27_enable(struct clk *clk)

{

	/*

	 * First, set up the 3.6864MHz clock on GPIO 27 for the SA-1111:
@@ -32,38 +44,24 @@ static void clk_gpio27_enable(void) 
	TUCR = TUCR_3_6864MHz;

}



static void clk_gpio27_disable(void)

static void clk_gpio27_disable(struct clk *clk)

{

	TUCR = 0;

	GPDR &= ~GPIO_32_768kHz;

	GAFR &= ~GPIO_32_768kHz;

}



static struct clk clk_gpio27;



static DEFINE_SPINLOCK(clocks_lock);



struct clk *clk_get(struct device *dev, const char *id)

{

	const char *devname = dev_name(dev);



	return strcmp(devname, "sa1111.0") ? ERR_PTR(-ENOENT) : &clk_gpio27;

}

EXPORT_SYMBOL(clk_get);



void clk_put(struct clk *clk)

{

}

EXPORT_SYMBOL(clk_put);



int clk_enable(struct clk *clk)

{

	unsigned long flags;



	if (clk) {

		spin_lock_irqsave(&clocks_lock, flags);

		if (clk->enabled++ == 0)

		clk_gpio27_enable();

			clk->ops->enable(clk);

		spin_unlock_irqrestore(&clocks_lock, flags);

	}



	return 0;

}

EXPORT_SYMBOL(clk_enable);
@@ -72,17 +70,31 @@ void clk_disable(struct clk *clk) 
{

	unsigned long flags;



	if (clk) {

		WARN_ON(clk->enabled == 0);



		spin_lock_irqsave(&clocks_lock, flags);

		if (--clk->enabled == 0)

		clk_gpio27_disable();

			clk->ops->disable(clk);

		spin_unlock_irqrestore(&clocks_lock, flags);

	}

}

EXPORT_SYMBOL(clk_disable);



unsigned long clk_get_rate(struct clk *clk)

const struct clkops clk_gpio27_ops = {

	.enable		= clk_gpio27_enable,

	.disable	= clk_gpio27_disable,

};



static DEFINE_CLK(gpio27, &clk_gpio27_ops);



static struct clk_lookup sa11xx_clkregs[] = {

	CLKDEV_INIT("sa1111.0", NULL, &clk_gpio27),

	CLKDEV_INIT("sa1100-rtc", NULL, NULL),

};



static int __init sa11xx_clk_init(void)

{

	return 3686400;

	clkdev_add_table(sa11xx_clkregs, ARRAY_SIZE(sa11xx_clkregs));

	return 0;

}

EXPORT_SYMBOL(clk_get_rate);
 
core_initcall(sa11xx_clk_init);