Commit 4afda5f6 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
Browse files

clk: qcom: gcc-msm8996: Remove RPM bus clocks 



The GCC driver contains clocks that are owned (meaning configured and
scaled) by the RPM core.

Remove them from Linux to stop interjecting the RPM's logic.

Fixes: b1e010c0 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230830-topic-rpmbusclocks8996gcc-v1-1-9e99bedcdc3b@linaro.org


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent ccd8ab03

drivers/clk/qcom/gcc-msm8996.c

+5 −232
Original line number Diff line number Diff line
@@ -244,71 +244,6 @@ static const struct clk_parent_data gcc_xo_gpll0_gpll4_gpll0_early_div[] = { 
	{ .hw = &gpll0_early_div.hw }

};



static const struct freq_tbl ftbl_system_noc_clk_src[] = {

	F(19200000, P_XO, 1, 0, 0),

	F(50000000, P_GPLL0_EARLY_DIV, 6, 0, 0),

	F(100000000, P_GPLL0, 6, 0, 0),

	F(150000000, P_GPLL0, 4, 0, 0),

	F(200000000, P_GPLL0, 3, 0, 0),

	F(240000000, P_GPLL0, 2.5, 0, 0),

	{ }

};



static struct clk_rcg2 system_noc_clk_src = {

	.cmd_rcgr = 0x0401c,

	.hid_width = 5,

	.parent_map = gcc_xo_gpll0_gpll0_early_div_map,

	.freq_tbl = ftbl_system_noc_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "system_noc_clk_src",

		.parent_data = gcc_xo_gpll0_gpll0_early_div,

		.num_parents = ARRAY_SIZE(gcc_xo_gpll0_gpll0_early_div),

		.ops = &clk_rcg2_ops,

	},

};



static const struct freq_tbl ftbl_config_noc_clk_src[] = {

	F(19200000, P_XO, 1, 0, 0),

	F(37500000, P_GPLL0, 16, 0, 0),

	F(75000000, P_GPLL0, 8, 0, 0),

	{ }

};



static struct clk_rcg2 config_noc_clk_src = {

	.cmd_rcgr = 0x0500c,

	.hid_width = 5,

	.parent_map = gcc_xo_gpll0_map,

	.freq_tbl = ftbl_config_noc_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "config_noc_clk_src",

		.parent_data = gcc_xo_gpll0,

		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),

		.ops = &clk_rcg2_ops,

	},

};



static const struct freq_tbl ftbl_periph_noc_clk_src[] = {

	F(19200000, P_XO, 1, 0, 0),

	F(37500000, P_GPLL0, 16, 0, 0),

	F(50000000, P_GPLL0, 12, 0, 0),

	F(75000000, P_GPLL0, 8, 0, 0),

	F(100000000, P_GPLL0, 6, 0, 0),

	{ }

};



static struct clk_rcg2 periph_noc_clk_src = {

	.cmd_rcgr = 0x06014,

	.hid_width = 5,

	.parent_map = gcc_xo_gpll0_map,

	.freq_tbl = ftbl_periph_noc_clk_src,

	.clkr.hw.init = &(struct clk_init_data){

		.name = "periph_noc_clk_src",

		.parent_data = gcc_xo_gpll0,

		.num_parents = ARRAY_SIZE(gcc_xo_gpll0),

		.ops = &clk_rcg2_ops,

	},

};



static const struct freq_tbl ftbl_usb30_master_clk_src[] = {

	F(19200000, P_XO, 1, 0, 0),

	F(120000000, P_GPLL0, 5, 0, 0),
@@ -1297,11 +1232,7 @@ static struct clk_branch gcc_mmss_noc_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_mmss_noc_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,

			.flags = CLK_IGNORE_UNUSED,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1464,11 +1395,6 @@ static struct clk_branch gcc_usb_phy_cfg_ahb2phy_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_usb_phy_cfg_ahb2phy_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1498,11 +1424,6 @@ static struct clk_branch gcc_sdcc1_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdcc1_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1549,11 +1470,6 @@ static struct clk_branch gcc_sdcc2_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdcc2_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1583,11 +1499,6 @@ static struct clk_branch gcc_sdcc3_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdcc3_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1617,11 +1528,6 @@ static struct clk_branch gcc_sdcc4_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_sdcc4_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1635,11 +1541,6 @@ static struct clk_branch gcc_blsp1_ahb_clk = { 
		.enable_mask = BIT(17),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_blsp1_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -1977,11 +1878,6 @@ static struct clk_branch gcc_blsp2_ahb_clk = { 
		.enable_mask = BIT(15),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_blsp2_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2318,11 +2214,6 @@ static struct clk_branch gcc_pdm_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pdm_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2353,11 +2244,6 @@ static struct clk_branch gcc_prng_ahb_clk = { 
		.enable_mask = BIT(13),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_prng_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2370,11 +2256,6 @@ static struct clk_branch gcc_tsif_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_tsif_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2422,11 +2303,6 @@ static struct clk_branch gcc_boot_rom_ahb_clk = { 
		.enable_mask = BIT(10),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_boot_rom_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2520,11 +2396,6 @@ static struct clk_branch gcc_pcie_0_slv_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_slv_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2537,11 +2408,6 @@ static struct clk_branch gcc_pcie_0_mstr_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_mstr_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2554,11 +2420,6 @@ static struct clk_branch gcc_pcie_0_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_0_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2606,11 +2467,6 @@ static struct clk_branch gcc_pcie_1_slv_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_slv_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2623,11 +2479,6 @@ static struct clk_branch gcc_pcie_1_mstr_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_mstr_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2640,11 +2491,6 @@ static struct clk_branch gcc_pcie_1_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_1_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2692,11 +2538,6 @@ static struct clk_branch gcc_pcie_2_slv_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_2_slv_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2709,11 +2550,6 @@ static struct clk_branch gcc_pcie_2_mstr_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_2_mstr_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2726,11 +2562,6 @@ static struct clk_branch gcc_pcie_2_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_2_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2778,11 +2609,6 @@ static struct clk_branch gcc_pcie_phy_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_pcie_phy_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -2829,11 +2655,6 @@ static struct clk_branch gcc_ufs_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_ufs_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3060,11 +2881,7 @@ static struct clk_branch gcc_aggre0_snoc_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_aggre0_snoc_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3077,11 +2894,7 @@ static struct clk_branch gcc_aggre0_cnoc_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_aggre0_cnoc_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3094,11 +2907,7 @@ static struct clk_branch gcc_smmu_aggre0_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_smmu_aggre0_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3111,11 +2920,7 @@ static struct clk_branch gcc_smmu_aggre0_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_smmu_aggre0_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL,

			.flags = CLK_IS_CRITICAL,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3162,10 +2967,6 @@ static struct clk_branch gcc_dcc_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_dcc_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3178,10 +2979,6 @@ static struct clk_branch gcc_aggre0_noc_mpu_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_aggre0_noc_mpu_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3194,11 +2991,6 @@ static struct clk_branch gcc_qspi_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_qspi_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&periph_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.flags = CLK_SET_RATE_PARENT,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3347,10 +3139,6 @@ static struct clk_branch gcc_mss_cfg_ahb_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_mss_cfg_ahb_clk",

			.parent_hws = (const struct clk_hw*[]){

				&config_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3363,10 +3151,6 @@ static struct clk_branch gcc_mss_mnoc_bimc_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_mss_mnoc_bimc_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3379,10 +3163,6 @@ static struct clk_branch gcc_mss_snoc_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_mss_snoc_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3395,10 +3175,6 @@ static struct clk_branch gcc_mss_q6_bimc_axi_clk = { 
		.enable_mask = BIT(0),

		.hw.init = &(struct clk_init_data){

			.name = "gcc_mss_q6_bimc_axi_clk",

			.parent_hws = (const struct clk_hw*[]){

				&system_noc_clk_src.clkr.hw,

			},

			.num_parents = 1,

			.ops = &clk_branch2_ops,

		},

	},
@@ -3495,9 +3271,6 @@ static struct clk_regmap *gcc_msm8996_clocks[] = { 
	[GPLL0] = &gpll0.clkr,

	[GPLL4_EARLY] = &gpll4_early.clkr,

	[GPLL4] = &gpll4.clkr,

	[SYSTEM_NOC_CLK_SRC] = &system_noc_clk_src.clkr,

	[CONFIG_NOC_CLK_SRC] = &config_noc_clk_src.clkr,

	[PERIPH_NOC_CLK_SRC] = &periph_noc_clk_src.clkr,

	[USB30_MASTER_CLK_SRC] = &usb30_master_clk_src.clkr,

	[USB30_MOCK_UTMI_CLK_SRC] = &usb30_mock_utmi_clk_src.clkr,

	[USB3_PHY_AUX_CLK_SRC] = &usb3_phy_aux_clk_src.clkr,