Commit 4b18a3ef authored by Peter Griffin's avatar Peter Griffin Committed by Krzysztof Kozlowski
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clk: samsung: gs101: add support for Display Process Unit (DPU) clocks 



cmu_dpu is the clock management unit used for the Display Process Unit
block. It generates clocks for image scaler, compressor etc.

Add support for the muxes, dividers and gates in cmu_dpu.

Signed-off-by: default avatarPeter Griffin <peter.griffin@linaro.org>
Reviewed-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Link: https://patch.msgid.link/20260113-dpu-clocks-v3-4-cb85424f2c72@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
parent 1d8fae66

drivers/clk/samsung/clk-gs101.c

+283 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
/* NOTE: Must be equal to the last clock ID increased by one */

#define CLKS_NR_TOP	(CLK_GOUT_CMU_TPU_UART + 1)

#define CLKS_NR_APM	(CLK_APM_PLL_DIV16_APM + 1)

#define CLKS_NR_DPU	(CLK_GOUT_DPU_SYSREG_DPU_PCLK + 1)

#define CLKS_NR_HSI0	(CLK_GOUT_HSI0_XIU_P_HSI0_ACLK + 1)

#define CLKS_NR_HSI2	(CLK_GOUT_HSI2_XIU_P_HSI2_ACLK + 1)

#define CLKS_NR_MISC	(CLK_GOUT_MISC_XIU_D_MISC_ACLK + 1)
@@ -1932,6 +1933,285 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { 
	.memclk_offset		= GS101_MEMCLK_OFFSET,

};



/* ---- CMU_DPU ------------------------------------------------------------- */



/* Register Offset definitions for CMU_DPU (0x1c000000) */

#define PLL_CON0_MUX_CLKCMU_DPU_BUS_USER					0x0600

#define PLL_CON1_MUX_CLKCMU_DPU_BUS_USER					0x0604

#define DPU_CMU_DPU_CONTROLLER_OPTION						0x0800

#define CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0					0x0810

#define CLK_CON_DIV_DIV_CLK_DPU_BUSP						0x1800

#define CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK			0x2000

#define CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK	0x2004

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM		0x2008

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA			0x200c

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP			0x2010

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK			0x2014

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK			0x2018

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK		0x201c

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK		0x2020

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK		0x2024

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK		0x2028

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK			0x202c

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK			0x2030

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK			0x2034

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK			0x2038

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK			0x203c

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK			0x2040

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK	0x2044

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK	0x2048

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK			0x204c

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK			0x2050

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK			0x2054

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK			0x2058

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK			0x205c

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK			0x2060

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1		0x2064

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2		0x2068

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1		0x206c

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2		0x2070

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1		0x2074

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2		0x2078

#define CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK			0x207c

#define PCH_CON_LHM_AXI_P_DPU_PCH						0x3000

#define PCH_CON_LHS_AXI_D0_DPU_PCH						0x3004

#define PCH_CON_LHS_AXI_D1_DPU_PCH						0x3008

#define PCH_CON_LHS_AXI_D2_DPU_PCH						0x300c

#define QCH_CON_DPUF_QCH_DPU_DMA						0x3010

#define QCH_CON_DPUF_QCH_DPU_DPP						0x3014

#define QCH_CON_DPU_CMU_DPU_QCH							0x301c

#define QCH_CON_D_TZPC_DPU_QCH							0x3020

#define QCH_CON_GPC_DPU_QCH							0x3024

#define QCH_CON_LHM_AXI_P_DPU_QCH						0x3028

#define QCH_CON_LHS_AXI_D0_DPU_QCH						0x302c

#define QCH_CON_LHS_AXI_D1_DPU_QCH						0x3030

#define QCH_CON_LHS_AXI_D2_DPU_QCH						0x3034

#define QCH_CON_PPMU_DPUD0_QCH							0x3038

#define QCH_CON_PPMU_DPUD1_QCH							0x303c

#define QCH_CON_PPMU_DPUD2_QCH							0x3040

#define QCH_CON_SSMT_DPU0_QCH							0x3044

#define QCH_CON_SSMT_DPU1_QCH							0x3048

#define QCH_CON_SSMT_DPU2_QCH							0x304c

#define QCH_CON_SYSMMU_DPUD0_QCH_S1						0x3050

#define QCH_CON_SYSMMU_DPUD0_QCH_S2						0x3054

#define QCH_CON_SYSMMU_DPUD1_QCH_S1						0x3058

#define QCH_CON_SYSMMU_DPUD1_QCH_S2						0x305c

#define QCH_CON_SYSMMU_DPUD2_QCH_S1						0x3060

#define QCH_CON_SYSMMU_DPUD2_QCH_S2						0x3064

#define QCH_CON_SYSREG_DPU_QCH							0x3068

#define QUEUE_CTRL_REG_BLK_DPU_CMU_DPU						0x3c00



static const unsigned long dpu_clk_regs[] __initconst = {

	PLL_CON0_MUX_CLKCMU_DPU_BUS_USER,

	PLL_CON1_MUX_CLKCMU_DPU_BUS_USER,

	DPU_CMU_DPU_CONTROLLER_OPTION,

	CLKOUT_CON_BLK_DPU_CMU_DPU_CLKOUT0,

	CLK_CON_DIV_DIV_CLK_DPU_BUSP,

	CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK,

	CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2,

	CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK,

	PCH_CON_LHM_AXI_P_DPU_PCH,

	PCH_CON_LHS_AXI_D0_DPU_PCH,

	PCH_CON_LHS_AXI_D1_DPU_PCH,

	PCH_CON_LHS_AXI_D2_DPU_PCH,

	QCH_CON_DPUF_QCH_DPU_DMA,

	QCH_CON_DPUF_QCH_DPU_DPP,

	QCH_CON_DPU_CMU_DPU_QCH,

	QCH_CON_D_TZPC_DPU_QCH,

	QCH_CON_GPC_DPU_QCH,

	QCH_CON_LHM_AXI_P_DPU_QCH,

	QCH_CON_LHS_AXI_D0_DPU_QCH,

	QCH_CON_LHS_AXI_D1_DPU_QCH,

	QCH_CON_LHS_AXI_D2_DPU_QCH,

	QCH_CON_PPMU_DPUD0_QCH,

	QCH_CON_PPMU_DPUD1_QCH,

	QCH_CON_PPMU_DPUD2_QCH,

	QCH_CON_SSMT_DPU0_QCH,

	QCH_CON_SSMT_DPU1_QCH,

	QCH_CON_SSMT_DPU2_QCH,

	QCH_CON_SYSMMU_DPUD0_QCH_S1,

	QCH_CON_SYSMMU_DPUD0_QCH_S2,

	QCH_CON_SYSMMU_DPUD1_QCH_S1,

	QCH_CON_SYSMMU_DPUD1_QCH_S2,

	QCH_CON_SYSMMU_DPUD2_QCH_S1,

	QCH_CON_SYSMMU_DPUD2_QCH_S2,

	QCH_CON_SYSREG_DPU_QCH,

	QUEUE_CTRL_REG_BLK_DPU_CMU_DPU,

};



/* List of parent clocks for Muxes in CMU_DPU */

PNAME(mout_dpu_bus_user_p)	= { "oscclk", "dout_cmu_dpu_bus" };



static const struct samsung_mux_clock dpu_mux_clks[] __initconst = {

	MUX(CLK_MOUT_DPU_BUS_USER, "mout_dpu_bus_user",

	    mout_dpu_bus_user_p, PLL_CON0_MUX_CLKCMU_DPU_BUS_USER, 4, 1),

};



static const struct samsung_div_clock dpu_div_clks[] __initconst = {

	DIV(CLK_DOUT_DPU_BUSP, "dout_dpu_busp", "mout_dpu_bus_user",

	    CLK_CON_DIV_DIV_CLK_DPU_BUSP, 0, 3),

};



static const struct samsung_gate_clock dpu_gate_clks[] __initconst = {

	GATE(CLK_GOUT_DPU_PCLK, "gout_dpu_dpu_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_CLK_BLK_DPU_UID_DPU_CMU_DPU_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_CLK_DPU_OSCCLK_CLK, "gout_dpu_clk_dpu_oscclk_clk",

	     "oscclk",

	     CLK_CON_GAT_CLK_BLK_DPU_UID_RSTNSYNC_CLK_DPU_OSCCLK_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_AD_APB_DPU_DMA_PCLKM, "gout_dpu_ad_apb_dpu_dma_pclkm",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_AD_APB_DPU_DMA_IPCLKPORT_PCLKM,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_DPUF_ACLK_DMA, "gout_dpu_dpuf_aclk_dma",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DMA, 21, 0, 0),

	GATE(CLK_GOUT_DPU_DPUF_ACLK_DPP, "gout_dpu_dpuf_aclk_dpp",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_DPUF_IPCLKPORT_ACLK_DPP, 21, 0, 0),

	GATE(CLK_GOUT_DPU_D_TZPC_DPU_PCLK, "gout_dpu_d_tzpc_dpu_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_D_TZPC_DPU_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_GPC_DPU_PCLK, "gout_dpu_gpc_dpu_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_GPC_DPU_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_LHM_AXI_P_DPU_I_CLK, "gout_dpu_lhm_axi_p_dpu_i_clk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_LHM_AXI_P_DPU_IPCLKPORT_I_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_LHS_AXI_D0_DPU_I_CLK, "gout_dpu_lhs_axi_d0_dpu_i_clk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D0_DPU_IPCLKPORT_I_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_LHS_AXI_D1_DPU_I_CLK, "gout_dpu_lhs_axi_d1_dpu_i_clk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D1_DPU_IPCLKPORT_I_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_LHS_AXI_D2_DPU_I_CLK, "gout_dpu_lhs_axi_d2_dpu_i_clk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_LHS_AXI_D2_DPU_IPCLKPORT_I_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_PPMU_DPUD0_ACLK, "gout_dpu_ppmu_dpud0_aclk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_ACLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_PPMU_DPUD0_PCLK, "gout_dpu_ppmu_dpud0_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD0_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_PPMU_DPUD1_ACLK, "gout_dpu_ppmu_dpud1_aclk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_ACLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_PPMU_DPUD1_PCLK, "gout_dpu_ppmu_dpud1_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD1_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_PPMU_DPUD2_ACLK, "gout_dpu_ppmu_dpud2_aclk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_ACLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_PPMU_DPUD2_PCLK, "gout_dpu_ppmu_dpud2_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_PPMU_DPUD2_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_CLK_DPU_BUSD_CLK, "gout_dpu_clk_dpu_busd_clk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSD_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_CLK_DPU_BUSP_CLK, "gout_dpu_clk_dpu_busp_clk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_RSTNSYNC_CLK_DPU_BUSP_IPCLKPORT_CLK,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_SSMT_DPU0_ACLK, "gout_dpu_ssmt_dpu0_aclk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_ACLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_SSMT_DPU0_PCLK, "gout_dpu_ssmt_dpu0_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU0_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_SSMT_DPU1_ACLK, "gout_dpu_ssmt_dpu1_aclk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_ACLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_SSMT_DPU1_PCLK, "gout_dpu_ssmt_dpu1_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU1_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_SSMT_DPU2_ACLK, "gout_dpu_ssmt_dpu2_aclk",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_ACLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_SSMT_DPU2_PCLK, "gout_dpu_ssmt_dpu2_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SSMT_DPU2_IPCLKPORT_PCLK, 21, 0, 0),

	GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S1, "gout_dpu_sysmmu_dpud0_clk_s1",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S1,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_SYSMMU_DPUD0_CLK_S2, "gout_dpu_sysmmu_dpud0_clk_s2",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD0_IPCLKPORT_CLK_S2,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S1, "gout_dpu_sysmmu_dpud1_clk_s1",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S1,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_SYSMMU_DPUD1_CLK_S2, "gout_dpu_sysmmu_dpud1_clk_s2",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD1_IPCLKPORT_CLK_S2,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S1, "gout_dpu_sysmmu_dpud2_clk_s1",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S1,

	     21, 0, 0),

	GATE(CLK_GOUT_DPU_SYSMMU_DPUD2_CLK_S2, "gout_dpu_sysmmu_dpud2_clk_s2",

	     "mout_dpu_bus_user",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSMMU_DPUD2_IPCLKPORT_CLK_S2, 21, 0, 0),

	GATE(CLK_GOUT_DPU_SYSREG_DPU_PCLK, "gout_dpu_sysreg_dpu_pclk",

	     "dout_dpu_busp",

	     CLK_CON_GAT_GOUT_BLK_DPU_UID_SYSREG_DPU_IPCLKPORT_PCLK, 21, 0, 0),

};



static const struct samsung_cmu_info dpu_cmu_info __initconst = {

	.mux_clks		= dpu_mux_clks,

	.nr_mux_clks		= ARRAY_SIZE(dpu_mux_clks),

	.div_clks		= dpu_div_clks,

	.nr_div_clks		= ARRAY_SIZE(dpu_div_clks),

	.gate_clks		= dpu_gate_clks,

	.nr_gate_clks		= ARRAY_SIZE(dpu_gate_clks),

	.nr_clk_ids		= CLKS_NR_DPU,

	.clk_regs		= dpu_clk_regs,

	.nr_clk_regs		= ARRAY_SIZE(dpu_clk_regs),

	.sysreg_clk_regs	= dcrg_memclk_sysreg,

	.nr_sysreg_clk_regs	= ARRAY_SIZE(dcrg_memclk_sysreg),

	.clk_name		= "bus",

	.auto_clock_gate        = true,

	.gate_dbg_offset        = GS101_GATE_DBG_OFFSET,

	.option_offset		= DPU_CMU_DPU_CONTROLLER_OPTION,

	.drcg_offset		= GS101_DRCG_EN_OFFSET,

};



/* ---- CMU_HSI0 ------------------------------------------------------------ */



/* Register Offset definitions for CMU_HSI0 (0x11000000) */
@@ -4443,6 +4723,9 @@ static const struct of_device_id gs101_cmu_of_match[] = { 
	{

		.compatible = "google,gs101-cmu-apm",

		.data = &apm_cmu_info,

	}, {

		.compatible = "google,gs101-cmu-dpu",

		.data = &dpu_cmu_info,

	}, {

		.compatible = "google,gs101-cmu-hsi0",

		.data = &hsi0_cmu_info,