Commit 4b27a33c authored by Alex Sierra's avatar Alex Sierra Committed by Alex Deucher
Browse files

drm/amdgpu: Force order between a read and write to the same address 



Setting register to force ordering to prevent read/write or write/read
hazards for un-cached modes.

Signed-off-by: default avatarAlex Sierra <alex.sierra@amd.com>
Acked-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Reviewed-by: default avatarFelix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.x
parent 884e9b08

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

+8 −0
Original line number Diff line number Diff line
@@ -89,6 +89,10 @@ MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin"); 
MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");

MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");



static const struct soc15_reg_golden golden_settings_gc_11_0[] = {

	SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)

};



static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =

{

	SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
@@ -304,6 +308,10 @@ static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev) 
	default:

		break;

	}

	soc15_program_register_sequence(adev,

					golden_settings_gc_11_0,

					(const u32)ARRAY_SIZE(golden_settings_gc_11_0));



}



static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,

drivers/gpu/drm/amd/include/asic_reg/gc/gc_11_0_0_offset.h

+2 −0
Original line number Diff line number Diff line
@@ -6369,6 +6369,8 @@ 
#define regTCP_INVALIDATE_BASE_IDX                                                                      1

#define regTCP_STATUS                                                                                   0x19a1

#define regTCP_STATUS_BASE_IDX                                                                          1

#define regTCP_CNTL                                                                                     0x19a2

#define regTCP_CNTL_BASE_IDX                                                                            1

#define regTCP_CNTL2                                                                                    0x19a3

#define regTCP_CNTL2_BASE_IDX                                                                           1

#define regTCP_DEBUG_INDEX                                                                              0x19a5