Commit 4b66be76 authored by Daniel Jurgens's avatar Daniel Jurgens Committed by Jakub Kicinski
Browse files

net/mlx5: Use set number of max EQs 



If a maximum number of EQs has been set for an SF, use that amount.

Signed-off-by: default avatarDaniel Jurgens <danielj@nvidia.com>
Reviewed-by: default avatarWilliam Tu <witu@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Signed-off-by: default avatarSaeed Mahameed <saeedm@nvidia.com>
Link: https://patch.msgid.link/20240712003310.355106-5-saeed@kernel.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent 20d80b95

drivers/net/ethernet/mellanox/mlx5/core/eq.c

+5 −2
Original line number Diff line number Diff line
@@ -1187,7 +1187,6 @@ static int get_num_eqs(struct mlx5_core_dev *dev) 
{

	struct mlx5_eq_table *eq_table = dev->priv.eq_table;

	int max_dev_eqs;

	int max_eqs_sf;

	int num_eqs;



	/* If ethernet is disabled we use just a single completion vector to
@@ -1202,7 +1201,11 @@ static int get_num_eqs(struct mlx5_core_dev *dev) 
	num_eqs = min_t(int, mlx5_irq_table_get_num_comp(eq_table->irq_table),

			max_dev_eqs - MLX5_MAX_ASYNC_EQS);

	if (mlx5_core_is_sf(dev)) {

		max_eqs_sf = min_t(int, MLX5_COMP_EQS_PER_SF,

		int max_eqs_sf = MLX5_CAP_GEN_2(dev, sf_eq_usage) ?

				 MLX5_CAP_GEN_2(dev, max_num_eqs_24b) :

				 MLX5_COMP_EQS_PER_SF;



		max_eqs_sf = min_t(int, max_eqs_sf,

				   mlx5_irq_table_get_sfs_vec(eq_table->irq_table));

		num_eqs = min_t(int, num_eqs, max_eqs_sf);

	}

drivers/net/ethernet/mellanox/mlx5/core/pci_irq.c

+4 −8
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#endif



#define MLX5_SFS_PER_CTRL_IRQ 64

#define MLX5_MAX_MSIX_PER_SF 256

#define MLX5_IRQ_CTRL_SF_MAX 8

/* min num of vectors for SFs to be enabled */

#define MLX5_IRQ_VEC_COMP_BASE_SF 2
@@ -589,8 +590,6 @@ static void irq_pool_free(struct mlx5_irq_pool *pool) 
static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pcif_vec)

{

	struct mlx5_irq_table *table = dev->priv.irq_table;

	int num_sf_ctrl_by_msix;

	int num_sf_ctrl_by_sfs;

	int num_sf_ctrl;

	int err;
@@ -608,10 +607,8 @@ static int irq_pools_init(struct mlx5_core_dev *dev, int sf_vec, int pcif_vec) 
	}



	/* init sf_ctrl_pool */

	num_sf_ctrl_by_msix = DIV_ROUND_UP(sf_vec, MLX5_COMP_EQS_PER_SF);

	num_sf_ctrl_by_sfs = DIV_ROUND_UP(mlx5_sf_max_functions(dev),

	num_sf_ctrl = DIV_ROUND_UP(mlx5_sf_max_functions(dev),

				   MLX5_SFS_PER_CTRL_IRQ);

	num_sf_ctrl = min_t(int, num_sf_ctrl_by_msix, num_sf_ctrl_by_sfs);

	num_sf_ctrl = min_t(int, MLX5_IRQ_CTRL_SF_MAX, num_sf_ctrl);

	table->sf_ctrl_pool = irq_pool_alloc(dev, pcif_vec, num_sf_ctrl,

					     "mlx5_sf_ctrl",
@@ -726,8 +723,7 @@ int mlx5_irq_table_create(struct mlx5_core_dev *dev) 


	total_vec = pcif_vec;

	if (mlx5_sf_max_functions(dev))

		total_vec += MLX5_IRQ_CTRL_SF_MAX +

			MLX5_COMP_EQS_PER_SF * mlx5_sf_max_functions(dev);

		total_vec += MLX5_MAX_MSIX_PER_SF * mlx5_sf_max_functions(dev);

	total_vec = min_t(int, total_vec, pci_msix_vec_count(dev->pdev));

	pcif_vec = min_t(int, pcif_vec, pci_msix_vec_count(dev->pdev));