Unverified Commit 4bf97069 authored by Charlie Jenkins's avatar Charlie Jenkins Committed by Palmer Dabbelt
Browse files

riscv: Add ghostwrite vulnerability 



Follow the patterns of the other architectures that use
GENERIC_CPU_VULNERABILITIES for riscv to introduce the ghostwrite
vulnerability and mitigation. The mitigation is to disable all vector
which is accomplished by clearing the bit from the cpufeature field.

Ghostwrite only affects thead c9xx CPUs that impelment xtheadvector, so
the vulerability will only be mitigated on these CPUs.

Signed-off-by: default avatarCharlie Jenkins <charlie@rivosinc.com>
Tested-by: default avatarYangyu Chen <cyy@cyyself.name>
Link: https://lore.kernel.org/r/20241113-xtheadvector-v11-14-236c22791ef9@rivosinc.com


Signed-off-by: default avatarPalmer Dabbelt <palmer@rivosinc.com>
parent c384c5d4

arch/riscv/Kconfig.errata

+11 −0
Original line number Diff line number Diff line
@@ -119,4 +119,15 @@ config ERRATA_THEAD_PMU 


	  If you don't know what to do here, say "Y".



config ERRATA_THEAD_GHOSTWRITE

	bool "Apply T-Head Ghostwrite errata"

	depends on ERRATA_THEAD && RISCV_ISA_XTHEADVECTOR

	default y

	help

	  The T-Head C9xx cores have a vulnerability in the xtheadvector

	  instruction set. When this errata is enabled, the CPUs will be probed

	  to determine if they are vulnerable and disable xtheadvector.



	  If you don't know what to do here, say "Y".



endmenu # "CPU errata selection"

arch/riscv/errata/thead/errata.c

+28 −0
Original line number Diff line number Diff line
@@ -10,6 +10,7 @@ 
#include <linux/string.h>

#include <linux/uaccess.h>

#include <asm/alternative.h>

#include <asm/bugs.h>

#include <asm/cacheflush.h>

#include <asm/cpufeature.h>

#include <asm/dma-noncoherent.h>
@@ -142,6 +143,31 @@ static bool errata_probe_pmu(unsigned int stage, 
	return true;

}



static bool errata_probe_ghostwrite(unsigned int stage,

				    unsigned long arch_id, unsigned long impid)

{

	if (!IS_ENABLED(CONFIG_ERRATA_THEAD_GHOSTWRITE))

		return false;



	/*

	 * target-c9xx cores report arch_id and impid as 0

	 *

	 * While ghostwrite may not affect all c9xx cores that implement

	 * xtheadvector, there is no futher granularity than c9xx. Assume

	 * vulnerable for this entire class of processors when xtheadvector is

	 * enabled.

	 */

	if (arch_id != 0 || impid != 0)

		return false;



	if (stage != RISCV_ALTERNATIVES_EARLY_BOOT)

		return false;



	ghostwrite_set_vulnerable();



	return true;

}



static u32 thead_errata_probe(unsigned int stage,

			      unsigned long archid, unsigned long impid)

{
@@ -155,6 +181,8 @@ static u32 thead_errata_probe(unsigned int stage, 
	if (errata_probe_pmu(stage, archid, impid))

		cpu_req_errata |= BIT(ERRATA_THEAD_PMU);



	errata_probe_ghostwrite(stage, archid, impid);



	return cpu_req_errata;

}

arch/riscv/include/asm/bugs.h

0 → 100644
+22 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: GPL-2.0-only */

/*

 * Interface for managing mitigations for riscv vulnerabilities.

 *

 * Copyright (C) 2024 Rivos Inc.

 */



#ifndef __ASM_BUGS_H

#define __ASM_BUGS_H



/* Watch out, ordering is important here. */

enum mitigation_state {

	UNAFFECTED,

	MITIGATED,

	VULNERABLE,

};



void ghostwrite_set_vulnerable(void);

bool ghostwrite_enable_mitigation(void);

enum mitigation_state ghostwrite_get_state(void);



#endif /* __ASM_BUGS_H */

arch/riscv/include/asm/errata_list.h

+2 −1
Original line number Diff line number Diff line
@@ -25,7 +25,8 @@ 
#ifdef CONFIG_ERRATA_THEAD

#define	ERRATA_THEAD_MAE 0

#define	ERRATA_THEAD_PMU 1

#define	ERRATA_THEAD_NUMBER 2

#define	ERRATA_THEAD_GHOSTWRITE 2

#define	ERRATA_THEAD_NUMBER 3

#endif



#ifdef __ASSEMBLY__

arch/riscv/kernel/Makefile

+2 −0
Original line number Diff line number Diff line
@@ -118,3 +118,5 @@ obj-$(CONFIG_COMPAT) += compat_vdso/ 
obj-$(CONFIG_64BIT)		+= pi/

obj-$(CONFIG_ACPI)		+= acpi.o

obj-$(CONFIG_ACPI_NUMA)	+= acpi_numa.o



obj-$(CONFIG_GENERIC_CPU_VULNERABILITIES) += bugs.o