Commit 4c27a32c authored by Geert Uytterhoeven's avatar Geert Uytterhoeven Committed by Rafael J. Wysocki
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dt-bindings: thermal: rcar-gen3-thermal: Add r8a779g0 support



Document support for the Thermal Sensor/Chip Internal Voltage
Monitor/Core Voltage Monitor (THS/CIVM/CVM) on the Renesas R-Car V4H
(R8A779G0) SoC.

Unlike most other R-Car Gen3 and Gen4 SoCs, it has 4 instead of 3
sensors, so increase the maximum number of reg tuples.
Just like other R-Car Gen4 SoCs, interrupts are not routed to the
INTC-AP but to the ECM.

Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: default avatarWolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/11f740522ec479011cc8eef6bb450603be394def.1675958665.git.geert+renesas@glider.be


Signed-off-by: default avatarDaniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: default avatarRafael J. Wysocki <rafael.j.wysocki@intel.com>
parent f5f633b1
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+3 −0
Original line number Diff line number Diff line
@@ -28,6 +28,7 @@ properties:
      - renesas,r8a77980-thermal # R-Car V3H
      - renesas,r8a779a0-thermal # R-Car V3U
      - renesas,r8a779f0-thermal # R-Car S4-8
      - renesas,r8a779g0-thermal # R-Car V4H

  reg: true

@@ -80,6 +81,7 @@ else:
        - description: TSC1 registers
        - description: TSC2 registers
        - description: TSC3 registers
        - description: TSC4 registers
  if:
    not:
      properties:
@@ -87,6 +89,7 @@ else:
          contains:
            enum:
              - renesas,r8a779f0-thermal
              - renesas,r8a779g0-thermal
  then:
    required:
      - interrupts