Commit 4c8e612c authored by Michael Chan's avatar Michael Chan Committed by Jakub Kicinski
Browse files

bnxt_en: Pass NQ ID to the FW when allocating RX/RX AGG rings 



Newer firmware can use the NQ ring ID associated with each RX/RX AGG
ring to enable PCIe Steering Tags on P5_PLUS chips.  When allocating
RX/RX AGG rings, pass along NQ ring ID for the firmware to use.  This
information helps optimize DMA writes by directing them to the cache
closer to the CPU consuming the data, potentially improving the
processing speed.  This change is backward-compatible with older
firmware, which will simply disregard the information.

Reviewed-by: default avatarHongguang Gao <hongguang.gao@broadcom.com>
Reviewed-by: default avatarAjit Khaparde <ajit.khaparde@broadcom.com>
Reviewed-by: default avatarMichal Swiatkowski <michal.swiatkowski@linux.intel.com>
Signed-off-by: default avatarAndy Gospodarek <andrew.gospodarek@broadcom.com>
Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Link: https://patch.msgid.link/20250213011240.1640031-8-michael.chan@broadcom.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent e1714de5

drivers/net/ethernet/broadcom/bnxt/bnxt.c

+3 −1
Original line number Diff line number Diff line
@@ -6949,7 +6949,8 @@ static void bnxt_set_rx_ring_params_p5(struct bnxt *bp, u32 ring_type, 
				       struct bnxt_ring_struct *ring)

{

	struct bnxt_ring_grp_info *grp_info = &bp->grp_info[ring->grp_idx];

	u32 enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID;

	u32 enables = RING_ALLOC_REQ_ENABLES_RX_BUF_SIZE_VALID |

		      RING_ALLOC_REQ_ENABLES_NQ_RING_ID_VALID;



	if (ring_type == HWRM_RING_ALLOC_AGG) {

		req->ring_type = RING_ALLOC_REQ_RING_TYPE_RX_AGG;
@@ -6963,6 +6964,7 @@ static void bnxt_set_rx_ring_params_p5(struct bnxt *bp, u32 ring_type, 
				cpu_to_le16(RING_ALLOC_REQ_FLAGS_RX_SOP_PAD);

	}

	req->stat_ctx_id = cpu_to_le32(grp_info->fw_stats_ctx);

	req->nq_ring_id = cpu_to_le16(grp_info->cp_fw_ring_id);

	req->enables |= cpu_to_le32(enables);

}