Commit 4caacd16 authored by Leo Li's avatar Leo Li Committed by Alex Deucher
Browse files

drm/amd/display: Do not elevate mem_type change to full update 



[Why]

There should not be any need to revalidate bandwidth on memory placement
change, since the fb is expected to be pinned to DCN-accessable memory
before scanout. For APU it's DRAM, and DGPU, it's VRAM. However, async
flips + memory type change needs to be rejected.

[How]

Do not set lock_and_validation_needed on mem_type change. Instead,
reject an async_flip request if the crtc's buffer(s) changed mem_type.

This may fix stuttering/corruption experienced with PSR SU and PSR1
panels, if the compositor allocates fbs in both VRAM carveout and GTT
and flips between them.

Fixes: a7c0cad0 ("drm/amd/display: ensure async flips are only accepted for fast updates")
Reviewed-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Signed-off-by: default avatarLeo Li <sunpeng.li@amd.com>
Signed-off-by: default avatarTom Chung <chiahsuan.chung@amd.com>
Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent aa6713fa

drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

+23 −6
Original line number Diff line number Diff line
@@ -11464,6 +11464,25 @@ static int dm_crtc_get_cursor_mode(struct amdgpu_device *adev, 
	return 0;

}



static bool amdgpu_dm_crtc_mem_type_changed(struct drm_device *dev,

					    struct drm_atomic_state *state,

					    struct drm_crtc_state *crtc_state)

{

	struct drm_plane *plane;

	struct drm_plane_state *new_plane_state, *old_plane_state;



	drm_for_each_plane_mask(plane, dev, crtc_state->plane_mask) {

		new_plane_state = drm_atomic_get_plane_state(state, plane);

		old_plane_state = drm_atomic_get_plane_state(state, plane);



		if (old_plane_state->fb && new_plane_state->fb &&

		    get_mem_type(old_plane_state->fb) != get_mem_type(new_plane_state->fb))

			return true;

	}



	return false;

}



/**

 * amdgpu_dm_atomic_check() - Atomic check implementation for AMDgpu DM.

 *
@@ -11661,10 +11680,6 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 


	/* Remove exiting planes if they are modified */

	for_each_oldnew_plane_in_descending_zpos(state, plane, old_plane_state, new_plane_state) {

		if (old_plane_state->fb && new_plane_state->fb &&

		    get_mem_type(old_plane_state->fb) !=

		    get_mem_type(new_plane_state->fb))

			lock_and_validation_needed = true;



		ret = dm_update_plane_state(dc, state, plane,

					    old_plane_state,
@@ -11959,9 +11974,11 @@ static int amdgpu_dm_atomic_check(struct drm_device *dev, 


		/*

		 * Only allow async flips for fast updates that don't change

		 * the FB pitch, the DCC state, rotation, etc.

		 * the FB pitch, the DCC state, rotation, mem_type, etc.

		 */

		if (new_crtc_state->async_flip && lock_and_validation_needed) {

		if (new_crtc_state->async_flip &&

		    (lock_and_validation_needed ||

		     amdgpu_dm_crtc_mem_type_changed(dev, state, new_crtc_state))) {

			drm_dbg_atomic(crtc->dev,

				       "[CRTC:%d:%s] async flips are only supported for fast updates\n",

				       crtc->base.id, crtc->name);