Commit 4cea0fc9 authored by Xiaomeng Hou's avatar Xiaomeng Hou Committed by Alex Deucher
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drm/amd/pm: add set_watermarks_table function for yellow carp 



Add callback function set_watermarks_table for yellow carp.

Acked-by: default avatarHuang Rui <ray.huang@amd.com>
Signed-off-by: default avatarXiaomeng Hou <Xiaomeng.Hou@amd.com>
Reviewed-by: default avatarKevin Wang <kevin1.wang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 77755dd3

drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

+61 −0
Original line number Diff line number Diff line
@@ -322,6 +322,66 @@ static int yellow_carp_read_sensor(struct smu_context *smu, 
	return ret;

}



static int yellow_carp_set_watermarks_table(struct smu_context *smu,

				struct pp_smu_wm_range_sets *clock_ranges)

{

	int i;

	int ret = 0;

	Watermarks_t *table = smu->smu_table.watermarks_table;



	if (!table || !clock_ranges)

		return -EINVAL;



	if (clock_ranges) {

		if (clock_ranges->num_reader_wm_sets > NUM_WM_RANGES ||

			clock_ranges->num_writer_wm_sets > NUM_WM_RANGES)

			return -EINVAL;



		for (i = 0; i < clock_ranges->num_reader_wm_sets; i++) {

			table->WatermarkRow[WM_DCFCLK][i].MinClock =

				clock_ranges->reader_wm_sets[i].min_drain_clk_mhz;

			table->WatermarkRow[WM_DCFCLK][i].MaxClock =

				clock_ranges->reader_wm_sets[i].max_drain_clk_mhz;

			table->WatermarkRow[WM_DCFCLK][i].MinMclk =

				clock_ranges->reader_wm_sets[i].min_fill_clk_mhz;

			table->WatermarkRow[WM_DCFCLK][i].MaxMclk =

				clock_ranges->reader_wm_sets[i].max_fill_clk_mhz;



			table->WatermarkRow[WM_DCFCLK][i].WmSetting =

				clock_ranges->reader_wm_sets[i].wm_inst;

		}



		for (i = 0; i < clock_ranges->num_writer_wm_sets; i++) {

			table->WatermarkRow[WM_SOCCLK][i].MinClock =

				clock_ranges->writer_wm_sets[i].min_fill_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MaxClock =

				clock_ranges->writer_wm_sets[i].max_fill_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MinMclk =

				clock_ranges->writer_wm_sets[i].min_drain_clk_mhz;

			table->WatermarkRow[WM_SOCCLK][i].MaxMclk =

				clock_ranges->writer_wm_sets[i].max_drain_clk_mhz;



			table->WatermarkRow[WM_SOCCLK][i].WmSetting =

				clock_ranges->writer_wm_sets[i].wm_inst;

		}



		smu->watermarks_bitmap |= WATERMARKS_EXIST;

	}



	/* pass data to smu controller */

	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

	     !(smu->watermarks_bitmap & WATERMARKS_LOADED)) {

		ret = smu_cmn_write_watermarks_table(smu);

		if (ret) {

			dev_err(smu->adev->dev, "Failed to update WMTABLE!");

			return ret;

		}

		smu->watermarks_bitmap |= WATERMARKS_LOADED;

	}



	return 0;

}



static const struct pptable_funcs yellow_carp_ppt_funcs = {

	.check_fw_status = smu_v13_0_1_check_fw_status,

	.check_fw_version = smu_v13_0_1_check_fw_version,
@@ -334,6 +394,7 @@ static const struct pptable_funcs yellow_carp_ppt_funcs = { 
	.set_default_dpm_table = smu_v13_0_1_set_default_dpm_tables,

	.read_sensor = yellow_carp_read_sensor,

	.is_dpm_running = yellow_carp_is_dpm_running,

	.set_watermarks_table = yellow_carp_set_watermarks_table,

	.get_enabled_mask = smu_cmn_get_enabled_32_bits_mask,

	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,

	.set_driver_table_location = smu_v13_0_1_set_driver_table_location,