Commit 4cf17132 authored by Bjorn Helgaas's avatar Bjorn Helgaas
Browse files

Merge branch 'pci/controller/dw-rockchip' 

- Prevent race between link training and register update via DBI by
  inhibiting link training after hot reset and link down (Wilfred Mallawa)

* pci/controller/dw-rockchip:
  PCI: dw-rockchip: Delay link training after hot reset in EP mode
parents f623d50c c0b93754

drivers/pci/controller/dwc/pcie-dw-rockchip.c

+12 −3
Original line number Diff line number Diff line
@@ -58,6 +58,8 @@ 


/* Hot Reset Control Register */

#define PCIE_CLIENT_HOT_RESET_CTRL	0x180

#define  PCIE_LTSSM_APP_DLY2_EN		BIT(1)

#define  PCIE_LTSSM_APP_DLY2_DONE	BIT(3)

#define  PCIE_LTSSM_ENABLE_ENHANCE	BIT(4)



/* LTSSM Status Register */
@@ -475,7 +477,7 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) 
	struct rockchip_pcie *rockchip = arg;

	struct dw_pcie *pci = &rockchip->pci;

	struct device *dev = pci->dev;

	u32 reg;

	u32 reg, val;



	reg = rockchip_pcie_readl_apb(rockchip, PCIE_CLIENT_INTR_STATUS_MISC);

	rockchip_pcie_writel_apb(rockchip, reg, PCIE_CLIENT_INTR_STATUS_MISC);
@@ -486,6 +488,10 @@ static irqreturn_t rockchip_pcie_ep_sys_irq_thread(int irq, void *arg) 
	if (reg & PCIE_LINK_REQ_RST_NOT_INT) {

		dev_dbg(dev, "hot reset or link-down reset\n");

		dw_pcie_ep_linkdown(&pci->ep);

		/* Stop delaying link training. */

		val = HIWORD_UPDATE_BIT(PCIE_LTSSM_APP_DLY2_DONE);

		rockchip_pcie_writel_apb(rockchip, val,

					 PCIE_CLIENT_HOT_RESET_CTRL);

	}



	if (reg & PCIE_RDLH_LINK_UP_CHGED) {
@@ -567,8 +573,11 @@ static int rockchip_pcie_configure_ep(struct platform_device *pdev, 
		return ret;

	}



	/* LTSSM enable control mode */

	val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE);

	/*

	 * LTSSM enable control mode, and automatically delay link training on

	 * hot reset/link-down reset.

	 */

	val = HIWORD_UPDATE_BIT(PCIE_LTSSM_ENABLE_ENHANCE | PCIE_LTSSM_APP_DLY2_EN);

	rockchip_pcie_writel_apb(rockchip, val, PCIE_CLIENT_HOT_RESET_CTRL);



	rockchip_pcie_writel_apb(rockchip, PCIE_CLIENT_EP_MODE,