Commit 4cf78e4f authored by Michael Chan's avatar Michael Chan Committed by David S. Miller
Browse files

[TG3]: add 5780 basic support 



Add 5780 PCI IDs, chip IDs, and other basic support.

Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 6b6a93c6

drivers/net/tg3.c

+48 −5
Original line number Diff line number Diff line
@@ -221,6 +221,10 @@ static struct pci_device_id tg3_pci_tbl[] = { 
	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5753F,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5780S,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_TIGON3_5781,

	  PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0UL },

	{ PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_9DXX,
@@ -508,6 +512,9 @@ static void tg3_switch_clocks(struct tg3 *tp) 
	u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);

	u32 orig_clock_ctrl;



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)

		return;



	orig_clock_ctrl = clock_ctrl;

	clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |

		       CLOCK_CTRL_CLKRUN_OENABLE |
@@ -1145,6 +1152,8 @@ static int tg3_set_power_state(struct tg3 *tp, int state) 
		     CLOCK_CTRL_ALTCLK |

		     CLOCK_CTRL_PWRDOWN_PLL133);

		udelay(40);

	} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

		/* do nothing */

	} else if (!((tp->tg3_flags2 & TG3_FLG2_5750_PLUS) &&

		     (tp->tg3_flags & TG3_FLAG_ENABLE_ASF))) {

		u32 newbits1, newbits2;
@@ -4056,6 +4065,29 @@ static int tg3_chip_reset(struct tg3 *tp) 
	val &= ~PCIX_CAPS_RELAXED_ORDERING;

	pci_write_config_dword(tp->pdev, TG3PCI_X_CAPS, val);



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

		u32 val;



		/* Chip reset on 5780 will reset MSI enable bit,

		 * so need to restore it.

		 */

		if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {

			u16 ctrl;



			pci_read_config_word(tp->pdev,

					     tp->msi_cap + PCI_MSI_FLAGS,

					     &ctrl);

			pci_write_config_word(tp->pdev,

					      tp->msi_cap + PCI_MSI_FLAGS,

					      ctrl | PCI_MSI_FLAGS_ENABLE);

			val = tr32(MSGINT_MODE);

			tw32(MSGINT_MODE, val | MSGINT_MODE_ENABLE);

		}



		val = tr32(MEMARB_MODE);

		tw32(MEMARB_MODE, val | MEMARB_MODE_ENABLE);



	} else

		tw32(MEMARB_MODE, MEMARB_MODE_ENABLE);



	if (tp->pci_chip_rev_id == CHIPREV_ID_5750_A3) {
@@ -5683,7 +5715,8 @@ static int tg3_reset_hw(struct tg3 *tp) 
	tw32(MAC_RCV_RULE_1,  0x86000004 & RCV_RULE_DISABLE_MASK);

	tw32(MAC_RCV_VALUE_1, 0xffffffff & RCV_RULE_DISABLE_MASK);



	if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS)

	if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&

	    (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5780))

		limit = 8;

	else

		limit = 16;
@@ -8928,6 +8961,10 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	if (tp->pci_chip_rev_id == CHIPREV_ID_5752_A0_HW)

		tp->pci_chip_rev_id = CHIPREV_ID_5752_A0;



	/* Find msi capability. */

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)

		tp->msi_cap = pci_find_capability(tp->pdev, PCI_CAP_ID_MSI);



	/* Initialize misc host control in PCI block. */

	tp->misc_host_ctrl |= (misc_ctrl_reg &

			       MISC_HOST_CTRL_CHIPREV);
@@ -8943,7 +8980,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) 
	tp->pci_bist         = (cacheline_sz_reg >> 24) & 0xff;



	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752 ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780)

		tp->tg3_flags2 |= TG3_FLG2_5750_PLUS;



	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) ||
@@ -9305,8 +9343,9 @@ static int __devinit tg3_get_device_address(struct tg3 *tp) 
#endif



	mac_offset = 0x7c;

	if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&

	    !(tp->tg3_flags & TG3_FLG2_SUN_570X)) {

	if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 &&

	     !(tp->tg3_flags & TG3_FLG2_SUN_570X)) ||

	    GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

		if (tr32(TG3PCI_DUAL_MAC_CTRL) & DUAL_MAC_CTRL_ID)

			mac_offset = 0xcc;

		if (tg3_nvram_lock(tp))
@@ -9620,6 +9659,9 @@ static int __devinit tg3_test_dma(struct tg3 *tp) 


			/* Set bit 23 to enable PCIX hw bug fix */

			tp->dma_rwctrl |= 0x009f0000;

		} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5780) {

			/* 5780 always in PCIX mode */

			tp->dma_rwctrl |= 0x00144000;

		} else {

			tp->dma_rwctrl |= 0x001b000f;

		}
@@ -9803,6 +9845,7 @@ static char * __devinit tg3_phy_string(struct tg3 *tp) 
	case PHY_ID_BCM5705:	return "5705";

	case PHY_ID_BCM5750:	return "5750";

	case PHY_ID_BCM5752:	return "5752";

	case PHY_ID_BCM5780:	return "5780";

	case PHY_ID_BCM8002:	return "8002/serdes";

	case 0:			return "serdes";

	default:		return "unknown";

drivers/net/tg3.h

+3 −0
Original line number Diff line number Diff line
@@ -136,6 +136,7 @@ 
#define   ASIC_REV_5705			 0x03

#define   ASIC_REV_5750			 0x04

#define   ASIC_REV_5752			 0x06

#define   ASIC_REV_5780			 0x08

#define  GET_CHIP_REV(CHIP_REV_ID)	((CHIP_REV_ID) >> 8)

#define   CHIPREV_5700_AX		 0x70

#define   CHIPREV_5700_BX		 0x71
@@ -2187,6 +2188,7 @@ struct tg3 { 
	u8				pci_bist;



	int				pm_cap;

	int				msi_cap;



	/* PHY info */

	u32				phy_id;
@@ -2200,6 +2202,7 @@ struct tg3 { 
#define PHY_ID_BCM5705			0x600081a0

#define PHY_ID_BCM5750			0x60008180

#define PHY_ID_BCM5752			0x60008100

#define PHY_ID_BCM5780			0x60008350

#define PHY_ID_BCM8002			0x60010140

#define PHY_ID_INVALID			0xffffffff

#define PHY_ID_REV_MASK			0x0000000f

include/linux/pci_ids.h

+2 −0
Original line number Diff line number Diff line
@@ -2098,6 +2098,8 @@ 
#define PCI_DEVICE_ID_TIGON3_5721	0x1659

#define PCI_DEVICE_ID_TIGON3_5705M	0x165d

#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e

#define PCI_DEVICE_ID_TIGON3_5780	0x166a

#define PCI_DEVICE_ID_TIGON3_5780S	0x166b

#define PCI_DEVICE_ID_TIGON3_5705F	0x166e

#define PCI_DEVICE_ID_TIGON3_5750	0x1676

#define PCI_DEVICE_ID_TIGON3_5751	0x1677