Commit 4d230aa2 authored by Karunika Choo's avatar Karunika Choo Committed by Boris Brezillon
Browse files

drm/panthor: Add 64-bit and poll register accessors 



This patch adds 64-bit register accessors to simplify register access in
Panthor. It also adds 32-bit and 64-bit variants for read_poll_timeout.

This patch also updates Panthor to use the new 64-bit accessors and poll
functions.

Reviewed-by: default avatarLiviu Dudau <liviu.dudau@arm.com>
Reviewed-by: default avatarSteven Price <steven.price@arm.com>
Reviewed-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: default avatarKarunika Choo <karunika.choo@arm.com>
Link: https://lore.kernel.org/r/20250606101835.41840-2-boris.brezillon@collabora.com


Signed-off-by: default avatarBoris Brezillon <boris.brezillon@collabora.com>
parent 94ac529a

drivers/gpu/drm/panthor/panthor_device.h

+71 −0
Original line number Diff line number Diff line
@@ -455,4 +455,75 @@ static int panthor_request_ ## __name ## _irq(struct panthor_device *ptdev, \ 


extern struct workqueue_struct *panthor_cleanup_wq;



static inline void gpu_write(struct panthor_device *ptdev, u32 reg, u32 data)

{

	writel(data, ptdev->iomem + reg);

}



static inline u32 gpu_read(struct panthor_device *ptdev, u32 reg)

{

	return readl(ptdev->iomem + reg);

}



static inline u32 gpu_read_relaxed(struct panthor_device *ptdev, u32 reg)

{

	return readl_relaxed(ptdev->iomem + reg);

}



static inline void gpu_write64(struct panthor_device *ptdev, u32 reg, u64 data)

{

	gpu_write(ptdev, reg, lower_32_bits(data));

	gpu_write(ptdev, reg + 4, upper_32_bits(data));

}



static inline u64 gpu_read64(struct panthor_device *ptdev, u32 reg)

{

	return (gpu_read(ptdev, reg) | ((u64)gpu_read(ptdev, reg + 4) << 32));

}



static inline u64 gpu_read64_relaxed(struct panthor_device *ptdev, u32 reg)

{

	return (gpu_read_relaxed(ptdev, reg) |

		((u64)gpu_read_relaxed(ptdev, reg + 4) << 32));

}



static inline u64 gpu_read64_counter(struct panthor_device *ptdev, u32 reg)

{

	u32 lo, hi1, hi2;

	do {

		hi1 = gpu_read(ptdev, reg + 4);

		lo = gpu_read(ptdev, reg);

		hi2 = gpu_read(ptdev, reg + 4);

	} while (hi1 != hi2);

	return lo | ((u64)hi2 << 32);

}



#define gpu_read_poll_timeout(dev, reg, val, cond, delay_us, timeout_us)	\

	read_poll_timeout(gpu_read, val, cond, delay_us, timeout_us, false,	\

			  dev, reg)



#define gpu_read_poll_timeout_atomic(dev, reg, val, cond, delay_us,		\

				     timeout_us)				\

	read_poll_timeout_atomic(gpu_read, val, cond, delay_us, timeout_us,	\

				 false, dev, reg)



#define gpu_read64_poll_timeout(dev, reg, val, cond, delay_us, timeout_us)	\

	read_poll_timeout(gpu_read64, val, cond, delay_us, timeout_us, false,	\

			  dev, reg)



#define gpu_read64_poll_timeout_atomic(dev, reg, val, cond, delay_us,		\

				       timeout_us)				\

	read_poll_timeout_atomic(gpu_read64, val, cond, delay_us, timeout_us,	\

				 false, dev, reg)



#define gpu_read_relaxed_poll_timeout_atomic(dev, reg, val, cond, delay_us,	\

					     timeout_us)			\

	read_poll_timeout_atomic(gpu_read_relaxed, val, cond, delay_us,		\

				 timeout_us, false, dev, reg)



#define gpu_read64_relaxed_poll_timeout(dev, reg, val, cond, delay_us,		\

					timeout_us)				\

	read_poll_timeout(gpu_read64_relaxed, val, cond, delay_us, timeout_us,	\

			  false, dev, reg)



#endif

drivers/gpu/drm/panthor/panthor_drv.c

+2 −2
Original line number Diff line number Diff line
@@ -772,8 +772,8 @@ static int panthor_query_timestamp_info(struct panthor_device *ptdev, 
#else

	arg->timestamp_frequency = 0;

#endif

	arg->current_timestamp = panthor_gpu_read_timestamp(ptdev);

	arg->timestamp_offset = panthor_gpu_read_timestamp_offset(ptdev);

	arg->current_timestamp = gpu_read64_counter(ptdev, GPU_TIMESTAMP_LO);

	arg->timestamp_offset = gpu_read64(ptdev, GPU_TIMESTAMP_OFFSET_LO);



	pm_runtime_put(ptdev->base.dev);

	return 0;

drivers/gpu/drm/panthor/panthor_fw.c

+5 −4
Original line number Diff line number Diff line
@@ -1063,7 +1063,7 @@ static void panthor_fw_stop(struct panthor_device *ptdev) 
	u32 status;



	gpu_write(ptdev, MCU_CONTROL, MCU_CONTROL_DISABLE);

	if (readl_poll_timeout(ptdev->iomem + MCU_STATUS, status,

	if (gpu_read_poll_timeout(ptdev, MCU_STATUS, status,

				  status == MCU_STATUS_DISABLED, 10, 100000))

		drm_err(&ptdev->base, "Failed to stop MCU");

}
@@ -1089,8 +1089,9 @@ void panthor_fw_pre_reset(struct panthor_device *ptdev, bool on_hang) 


		panthor_fw_update_reqs(glb_iface, req, GLB_HALT, GLB_HALT);

		gpu_write(ptdev, CSF_DOORBELL(CSF_GLB_DOORBELL_ID), 1);

		if (!readl_poll_timeout(ptdev->iomem + MCU_STATUS, status,

					status == MCU_STATUS_HALT, 10, 100000)) {

		if (!gpu_read_poll_timeout(ptdev, MCU_STATUS, status,

					   status == MCU_STATUS_HALT, 10,

					   100000)) {

			ptdev->reset.fast = true;

		} else {

			drm_warn(&ptdev->base, "Failed to cleanly suspend MCU");

drivers/gpu/drm/panthor/panthor_gpu.c

+35 −124
Original line number Diff line number Diff line
@@ -108,14 +108,9 @@ static void panthor_gpu_init_info(struct panthor_device *ptdev) 


	ptdev->gpu_info.as_present = gpu_read(ptdev, GPU_AS_PRESENT);



	ptdev->gpu_info.shader_present = gpu_read(ptdev, GPU_SHADER_PRESENT_LO);

	ptdev->gpu_info.shader_present |= (u64)gpu_read(ptdev, GPU_SHADER_PRESENT_HI) << 32;



	ptdev->gpu_info.tiler_present = gpu_read(ptdev, GPU_TILER_PRESENT_LO);

	ptdev->gpu_info.tiler_present |= (u64)gpu_read(ptdev, GPU_TILER_PRESENT_HI) << 32;



	ptdev->gpu_info.l2_present = gpu_read(ptdev, GPU_L2_PRESENT_LO);

	ptdev->gpu_info.l2_present |= (u64)gpu_read(ptdev, GPU_L2_PRESENT_HI) << 32;

	ptdev->gpu_info.shader_present = gpu_read64(ptdev, GPU_SHADER_PRESENT_LO);

	ptdev->gpu_info.tiler_present = gpu_read64(ptdev, GPU_TILER_PRESENT_LO);

	ptdev->gpu_info.l2_present = gpu_read64(ptdev, GPU_L2_PRESENT_LO);



	arch_major = GPU_ARCH_MAJOR(ptdev->gpu_info.gpu_id);

	product_major = GPU_PROD_MAJOR(ptdev->gpu_info.gpu_id);
@@ -154,8 +149,7 @@ static void panthor_gpu_irq_handler(struct panthor_device *ptdev, u32 status) 


	if (status & GPU_IRQ_FAULT) {

		u32 fault_status = gpu_read(ptdev, GPU_FAULT_STATUS);

		u64 address = ((u64)gpu_read(ptdev, GPU_FAULT_ADDR_HI) << 32) |

			      gpu_read(ptdev, GPU_FAULT_ADDR_LO);

		u64 address = gpu_read64(ptdev, GPU_FAULT_ADDR_LO);



		drm_warn(&ptdev->base, "GPU Fault 0x%08x (%s) at 0x%016llx\n",

			 fault_status, panthor_exception_name(ptdev, fault_status & 0xFF),
@@ -246,46 +240,28 @@ int panthor_gpu_block_power_off(struct panthor_device *ptdev, 
				u32 pwroff_reg, u32 pwrtrans_reg,

				u64 mask, u32 timeout_us)

{

	u32 val, i;

	u32 val;

	int ret;



	for (i = 0; i < 2; i++) {

		u32 mask32 = mask >> (i * 32);



		if (!mask32)

			continue;



		ret = readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4),

						 val, !(mask32 & val),

						 100, timeout_us);

	ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,

					      !(mask & val), 100, timeout_us);

	if (ret) {

			drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition",

				blk_name, mask);

		drm_err(&ptdev->base,

			"timeout waiting on %s:%llx power transition", blk_name,

			mask);

		return ret;

	}

	}



	if (mask & GENMASK(31, 0))

		gpu_write(ptdev, pwroff_reg, mask);

	gpu_write64(ptdev, pwroff_reg, mask);



	if (mask >> 32)

		gpu_write(ptdev, pwroff_reg + 4, mask >> 32);



	for (i = 0; i < 2; i++) {

		u32 mask32 = mask >> (i * 32);



		if (!mask32)

			continue;



		ret = readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4),

						 val, !(mask32 & val),

						 100, timeout_us);

	ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,

					      !(mask & val), 100, timeout_us);

	if (ret) {

			drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition",

				blk_name, mask);

		drm_err(&ptdev->base,

			"timeout waiting on %s:%llx power transition", blk_name,

			mask);

		return ret;

	}

	}



	return 0;

}
@@ -307,46 +283,27 @@ int panthor_gpu_block_power_on(struct panthor_device *ptdev, 
			       u32 pwron_reg, u32 pwrtrans_reg,

			       u32 rdy_reg, u64 mask, u32 timeout_us)

{

	u32 val, i;

	u32 val;

	int ret;



	for (i = 0; i < 2; i++) {

		u32 mask32 = mask >> (i * 32);



		if (!mask32)

			continue;



		ret = readl_relaxed_poll_timeout(ptdev->iomem + pwrtrans_reg + (i * 4),

						 val, !(mask32 & val),

						 100, timeout_us);

	ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,

					      !(mask & val), 100, timeout_us);

	if (ret) {

			drm_err(&ptdev->base, "timeout waiting on %s:%llx power transition",

				blk_name, mask);

		drm_err(&ptdev->base,

			"timeout waiting on %s:%llx power transition", blk_name,

			mask);

		return ret;

	}

	}



	if (mask & GENMASK(31, 0))

		gpu_write(ptdev, pwron_reg, mask);



	if (mask >> 32)

		gpu_write(ptdev, pwron_reg + 4, mask >> 32);



	for (i = 0; i < 2; i++) {

		u32 mask32 = mask >> (i * 32);

	gpu_write64(ptdev, pwron_reg, mask);



		if (!mask32)

			continue;



		ret = readl_relaxed_poll_timeout(ptdev->iomem + rdy_reg + (i * 4),

						 val, (mask32 & val) == mask32,

						 100, timeout_us);

	ret = gpu_read64_relaxed_poll_timeout(ptdev, pwrtrans_reg, val,

					      !(mask & val), 100, timeout_us);

	if (ret) {

		drm_err(&ptdev->base, "timeout waiting on %s:%llx readiness",

			blk_name, mask);

		return ret;

	}

	}



	return 0;

}
@@ -494,49 +451,3 @@ void panthor_gpu_resume(struct panthor_device *ptdev) 
	panthor_gpu_l2_power_on(ptdev);

}

/**

 * panthor_gpu_read_64bit_counter() - Read a 64-bit counter at a given offset.

 * @ptdev: Device.

 * @reg: The offset of the register to read.

 *

 * Return: The counter value.

 */

static u64

panthor_gpu_read_64bit_counter(struct panthor_device *ptdev, u32 reg)

{

	u32 hi, lo;



	do {

		hi = gpu_read(ptdev, reg + 0x4);

		lo = gpu_read(ptdev, reg);

	} while (hi != gpu_read(ptdev, reg + 0x4));



	return ((u64)hi << 32) | lo;

}



/**

 * panthor_gpu_read_timestamp() - Read the timestamp register.

 * @ptdev: Device.

 *

 * Return: The GPU timestamp value.

 */

u64 panthor_gpu_read_timestamp(struct panthor_device *ptdev)

{

	return panthor_gpu_read_64bit_counter(ptdev, GPU_TIMESTAMP_LO);

}



/**

 * panthor_gpu_read_timestamp_offset() - Read the timestamp offset register.

 * @ptdev: Device.

 *

 * Return: The GPU timestamp offset value.

 */

u64 panthor_gpu_read_timestamp_offset(struct panthor_device *ptdev)

{

	u32 hi, lo;



	hi = gpu_read(ptdev, GPU_TIMESTAMP_OFFSET_HI);

	lo = gpu_read(ptdev, GPU_TIMESTAMP_OFFSET_LO);



	return ((u64)hi << 32) | lo;

}

drivers/gpu/drm/panthor/panthor_gpu.h

+0 −2
Original line number Diff line number Diff line
@@ -50,7 +50,5 @@ int panthor_gpu_l2_power_on(struct panthor_device *ptdev); 
int panthor_gpu_flush_caches(struct panthor_device *ptdev,

			     u32 l2, u32 lsc, u32 other);

int panthor_gpu_soft_reset(struct panthor_device *ptdev);

u64 panthor_gpu_read_timestamp(struct panthor_device *ptdev);

u64 panthor_gpu_read_timestamp_offset(struct panthor_device *ptdev);



#endif