Unverified Commit 4d244122 authored by Kaustabh Chakraborty's avatar Kaustabh Chakraborty Committed by Inki Dae
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drm/bridge: samsung-dsim: allow configuring the MAIN_VSA offset 



The MAIN_VSA offset of DSIM_MSYNC is hardcoded to a 22-bit offset, but
Exynos7870's DSIM has it in a 16-bit offset as per the downstream kernel
sources.

In order to support both, move this offset value to the driver data
struct and define it for every driver compatible. Reference the value
from there instead, in functions wherever required.

Signed-off-by: default avatarKaustabh Chakraborty <kauschluss@disroot.org>
Signed-off-by: default avatarInki Dae <inki.dae@samsung.com>
parent f6ba4c15

drivers/gpu/drm/bridge/samsung-dsim.c

+10 −3
Original line number Diff line number Diff line
@@ -125,9 +125,9 @@ 
#define DSIM_MAIN_HBP_MASK		((0xffff) << 0)



/* DSIM_MSYNC */

#define DSIM_MAIN_VSA(x)		((x) << 22)

#define DSIM_MAIN_VSA(x, offset)	((x) << offset)

#define DSIM_MAIN_HSA(x)		((x) << 0)

#define DSIM_MAIN_VSA_MASK		((0x3ff) << 22)

#define DSIM_MAIN_VSA_MASK(offset)	((0x3ff) << offset)

#define DSIM_MAIN_HSA_MASK		((0xffff) << 0)



/* DSIM_SDRESOL */
@@ -423,6 +423,7 @@ static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { 
	.lane_esc_clk_bit = 19,

	.lane_esc_data_offset = 20,

	.pll_p_offset = 13,

	.main_vsa_offset = 22,

	.reg_values = reg_values,

	.pll_fin_min = 6,

	.pll_fin_max = 12,
@@ -449,6 +450,7 @@ static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { 
	.lane_esc_clk_bit = 19,

	.lane_esc_data_offset = 20,

	.pll_p_offset = 13,

	.main_vsa_offset = 22,

	.reg_values = reg_values,

	.pll_fin_min = 6,

	.pll_fin_max = 12,
@@ -473,6 +475,7 @@ static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { 
	.lane_esc_clk_bit = 19,

	.lane_esc_data_offset = 20,

	.pll_p_offset = 13,

	.main_vsa_offset = 22,

	.reg_values = reg_values,

	.pll_fin_min = 6,

	.pll_fin_max = 12,
@@ -497,6 +500,7 @@ static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { 
	.lane_esc_clk_bit = 19,

	.lane_esc_data_offset = 20,

	.pll_p_offset = 13,

	.main_vsa_offset = 22,

	.reg_values = exynos5433_reg_values,

	.pll_fin_min = 6,

	.pll_fin_max = 12,
@@ -521,6 +525,7 @@ static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { 
	.lane_esc_clk_bit = 19,

	.lane_esc_data_offset = 20,

	.pll_p_offset = 13,

	.main_vsa_offset = 22,

	.reg_values = exynos5422_reg_values,

	.pll_fin_min = 6,

	.pll_fin_max = 12,
@@ -549,6 +554,7 @@ static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { 
	 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c

	 */

	.pll_p_offset = 14,

	.main_vsa_offset = 22,

	.reg_values = imx8mm_dsim_reg_values,

	.pll_fin_min = 2,

	.pll_fin_max = 30,
@@ -1041,6 +1047,7 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) 
{

	struct drm_display_mode *m = &dsi->mode;

	unsigned int num_bits_resol = dsi->driver_data->num_bits_resol;

	unsigned int main_vsa_offset = dsi->driver_data->main_vsa_offset;

	u32 reg;



	if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
@@ -1067,7 +1074,7 @@ static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) 
		reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp);

		samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg);



		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start)

		reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start, main_vsa_offset)

			| DSIM_MAIN_HSA(hsa);

		samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg);

	}

include/drm/bridge/samsung-dsim.h

+1 −0
Original line number Diff line number Diff line
@@ -70,6 +70,7 @@ struct samsung_dsim_driver_data { 
	unsigned int lane_esc_clk_bit;

	unsigned int lane_esc_data_offset;

	unsigned int pll_p_offset;

	unsigned int main_vsa_offset;

	const unsigned int *reg_values;

	unsigned int pll_fin_min;

	unsigned int pll_fin_max;