Commit 4d2b0369 authored by Michael Neuling's avatar Michael Neuling Committed by Paul Walmsley
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riscv: errata: Fix bitwise vs logical AND in MIPS errata patching 



The condition checking whether a specific errata needs patching uses
logical AND (&&) instead of bitwise AND (&). Since logical AND only
checks that both operands are non-zero, this causes all errata patches
to be applied whenever any single errata is detected, rather than only
applying the matching one.

The SiFive errata implementation correctly uses bitwise AND for the same
check.

Fixes: 0b0ca959 ("riscv: errata: Fix the PAUSE Opcode for MIPS P8700")
Signed-off-by: default avatarMichael Neuling <mikey@neuling.org>
Assisted-by: Cursor:claude-4.6-opus-high-thinking
Link: https://patch.msgid.link/20260409091143.1348853-2-mikey@neuling.org


[pjw@kernel.org: fixed checkpatch warning]
Signed-off-by: default avatarPaul Walmsley <pjw@kernel.org>
parent a2e5b588

arch/riscv/errata/mips/errata.c

+1 −1
Original line number Diff line number Diff line
@@ -57,7 +57,7 @@ void mips_errata_patch_func(struct alt_entry *begin, struct alt_entry *end, 
		}



		tmp = (1U << alt->patch_id);

		if (cpu_req_errata && tmp) {

		if (cpu_req_errata & tmp) {

			mutex_lock(&text_mutex);

			patch_text_nosync(ALT_OLD_PTR(alt), ALT_ALT_PTR(alt),

					  alt->alt_len);