Commit 4d513329 authored by Lorenzo Bianconi's avatar Lorenzo Bianconi Committed by Jakub Kicinski
Browse files

net: airoha: Use gdm port enum value whenever possible 



Use AIROHA_GDMx_IDX enum value whenever possible.
This patch is just cosmetic changes and does not introduce any logic one.

Signed-off-by: default avatarLorenzo Bianconi <lorenzo@kernel.org>
Link: https://patch.msgid.link/20260105-airoha-use-port-idx-enum-v1-1-503ca5763858@kernel.org


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parent e9cd04b2

drivers/net/ethernet/airoha/airoha_eth.c

+21 −19
Original line number Diff line number Diff line
@@ -108,11 +108,11 @@ static int airoha_set_vip_for_gdm_port(struct airoha_gdm_port *port, 
	u32 vip_port;



	switch (port->id) {

	case 3:

	case AIROHA_GDM3_IDX:

		/* FIXME: handle XSI_PCIE1_PORT */

		vip_port = XSI_PCIE0_VIP_PORT_MASK;

		break;

	case 4:

	case AIROHA_GDM4_IDX:

		/* FIXME: handle XSI_USB_PORT */

		vip_port = XSI_ETH_VIP_PORT_MASK;

		break;
@@ -514,8 +514,8 @@ static int airoha_fe_init(struct airoha_eth *eth) 
		      FIELD_PREP(IP_ASSEMBLE_PORT_MASK, 0) |

		      FIELD_PREP(IP_ASSEMBLE_NBQ_MASK, 22));



	airoha_fe_set(eth, REG_GDM_FWD_CFG(3), GDM_PAD_EN_MASK);

	airoha_fe_set(eth, REG_GDM_FWD_CFG(4), GDM_PAD_EN_MASK);

	airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM3_IDX), GDM_PAD_EN_MASK);

	airoha_fe_set(eth, REG_GDM_FWD_CFG(AIROHA_GDM4_IDX), GDM_PAD_EN_MASK);



	airoha_fe_crsn_qsel_init(eth);
@@ -1690,27 +1690,29 @@ static int airhoha_set_gdm2_loopback(struct airoha_gdm_port *port) 
	/* Forward the traffic to the proper GDM port */

	pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3

					       : FE_PSE_PORT_GDM4;

	airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(2), pse_port);

	airoha_fe_clear(eth, REG_GDM_FWD_CFG(2), GDM_STRIP_CRC_MASK);

	airoha_set_gdm_port_fwd_cfg(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX),

				    pse_port);

	airoha_fe_clear(eth, REG_GDM_FWD_CFG(AIROHA_GDM2_IDX),

			GDM_STRIP_CRC_MASK);



	/* Enable GDM2 loopback */

	airoha_fe_wr(eth, REG_GDM_TXCHN_EN(2), 0xffffffff);

	airoha_fe_wr(eth, REG_GDM_RXCHN_EN(2), 0xffff);

	airoha_fe_wr(eth, REG_GDM_TXCHN_EN(AIROHA_GDM2_IDX), 0xffffffff);

	airoha_fe_wr(eth, REG_GDM_RXCHN_EN(AIROHA_GDM2_IDX), 0xffff);



	chan = port->id == AIROHA_GDM3_IDX ? airoha_is_7581(eth) ? 4 : 3 : 0;

	airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(2),

	airoha_fe_rmw(eth, REG_GDM_LPBK_CFG(AIROHA_GDM2_IDX),

		      LPBK_CHAN_MASK | LPBK_MODE_MASK | LPBK_EN_MASK,

		      FIELD_PREP(LPBK_CHAN_MASK, chan) |

		      LBK_GAP_MODE_MASK | LBK_LEN_MODE_MASK |

		      LBK_CHAN_MODE_MASK | LPBK_EN_MASK);

	airoha_fe_rmw(eth, REG_GDM_LEN_CFG(2),

	airoha_fe_rmw(eth, REG_GDM_LEN_CFG(AIROHA_GDM2_IDX),

		      GDM_SHORT_LEN_MASK | GDM_LONG_LEN_MASK,

		      FIELD_PREP(GDM_SHORT_LEN_MASK, 60) |

		      FIELD_PREP(GDM_LONG_LEN_MASK, AIROHA_MAX_MTU));



	/* Disable VIP and IFC for GDM2 */

	airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(2));

	airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(2));

	airoha_fe_clear(eth, REG_FE_VIP_PORT_EN, BIT(AIROHA_GDM2_IDX));

	airoha_fe_clear(eth, REG_FE_IFC_PORT_EN, BIT(AIROHA_GDM2_IDX));



	/* XXX: handle XSI_USB_PORT and XSI_PCE1_PORT */

	nbq = port->id == AIROHA_GDM3_IDX && airoha_is_7581(eth) ? 4 : 0;
@@ -1746,8 +1748,8 @@ static int airoha_dev_init(struct net_device *dev) 
	airoha_set_macaddr(port, dev->dev_addr);



	switch (port->id) {

	case 3:

	case 4:

	case AIROHA_GDM3_IDX:

	case AIROHA_GDM4_IDX:

		/* If GDM2 is active we can't enable loopback */

		if (!eth->ports[1]) {

			int err;
@@ -1757,7 +1759,7 @@ static int airoha_dev_init(struct net_device *dev) 
				return err;

		}

		fallthrough;

	case 2:

	case AIROHA_GDM2_IDX:

		if (airoha_ppe_is_enabled(eth, 1)) {

			/* For PPE2 always use secondary cpu port. */

			fe_cpu_port = FE_PSE_PORT_CDM2;
@@ -3101,14 +3103,14 @@ static const char * const en7581_xsi_rsts_names[] = { 
static int airoha_en7581_get_src_port_id(struct airoha_gdm_port *port, int nbq)

{

	switch (port->id) {

	case 3:

	case AIROHA_GDM3_IDX:

		/* 7581 SoC supports PCIe serdes on GDM3 port */

		if (nbq == 4)

			return HSGMII_LAN_7581_PCIE0_SRCPORT;

		if (nbq == 5)

			return HSGMII_LAN_7581_PCIE1_SRCPORT;

		break;

	case 4:

	case AIROHA_GDM4_IDX:

		/* 7581 SoC supports eth and usb serdes on GDM4 port */

		if (!nbq)

			return HSGMII_LAN_7581_ETH_SRCPORT;
@@ -3132,12 +3134,12 @@ static const char * const an7583_xsi_rsts_names[] = { 
static int airoha_an7583_get_src_port_id(struct airoha_gdm_port *port, int nbq)

{

	switch (port->id) {

	case 3:

	case AIROHA_GDM3_IDX:

		/* 7583 SoC supports eth serdes on GDM3 port */

		if (!nbq)

			return HSGMII_LAN_7583_ETH_SRCPORT;

		break;

	case 4:

	case AIROHA_GDM4_IDX:

		/* 7583 SoC supports PCIe and USB serdes on GDM4 port */

		if (!nbq)

			return HSGMII_LAN_7583_PCIE_SRCPORT;