Commit 4d588d32 authored by Pavan Chebbi's avatar Pavan Chebbi Committed by David S. Miller
Browse files

bnxt_en: Add BCM5760X specific PHC registers mapping



BCM5760X firmware will advertise direct 64-bit PHC registers access
for the driver from BAR0.

Make the necessary changes in handling HWRM_PORT_MAC_PTP_QCFG's
response and PHC register mapping for 5760X chips.

Signed-off-by: default avatarPavan Chebbi <pavan.chebbi@broadcom.com>
Signed-off-by: default avatarMichael Chan <michael.chan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 1d294b4f
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+8 −4
Original line number Diff line number Diff line
@@ -9011,7 +9011,7 @@ static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
	u8 flags;
	int rc;

	if (bp->hwrm_spec_code < 0x10801 || !BNXT_CHIP_P5(bp)) {
	if (bp->hwrm_spec_code < 0x10801 || !BNXT_CHIP_P5_PLUS(bp)) {
		rc = -ENODEV;
		goto no_ptp;
	}
@@ -9027,7 +9027,8 @@ static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
		goto exit;

	flags = resp->flags;
	if (!(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) {
	if (BNXT_CHIP_P5_AND_MINUS(bp) &&
	    !(flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS)) {
		rc = -ENODEV;
		goto exit;
	}
@@ -9040,10 +9041,13 @@ static int __bnxt_hwrm_ptp_qcfg(struct bnxt *bp)
		ptp->bp = bp;
		bp->ptp_cfg = ptp;
	}
	if (flags & PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK) {

	if (flags &
	    (PORT_MAC_PTP_QCFG_RESP_FLAGS_PARTIAL_DIRECT_ACCESS_REF_CLOCK |
	     PORT_MAC_PTP_QCFG_RESP_FLAGS_64B_PHC_TIME)) {
		ptp->refclk_regs[0] = le32_to_cpu(resp->ts_ref_clock_reg_lower);
		ptp->refclk_regs[1] = le32_to_cpu(resp->ts_ref_clock_reg_upper);
	} else if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
	} else if (BNXT_CHIP_P5(bp)) {
		ptp->refclk_regs[0] = BNXT_TS_REG_TIMESYNC_TS0_LOWER;
		ptp->refclk_regs[1] = BNXT_TS_REG_TIMESYNC_TS0_UPPER;
	} else {
+8 −0
Original line number Diff line number Diff line
@@ -2263,9 +2263,17 @@ struct bnxt {
	 (BNXT_CHIP_NUM_58700((bp)->chip_num) &&	\
	  !BNXT_CHIP_TYPE_NITRO_A0(bp)))

/* Chip class phase 3.x */
#define BNXT_CHIP_P3(bp)			\
	(BNXT_CHIP_NUM_57X0X((bp)->chip_num) ||	\
	 BNXT_CHIP_TYPE_NITRO_A0(bp))

#define BNXT_CHIP_P4_PLUS(bp)			\
	(BNXT_CHIP_P4(bp) || BNXT_CHIP_P5_PLUS(bp))

#define BNXT_CHIP_P5_AND_MINUS(bp)		\
	(BNXT_CHIP_P3(bp) || BNXT_CHIP_P4(bp) || BNXT_CHIP_P5(bp))

	struct bnxt_aux_priv	*aux_priv;
	struct bnxt_en_dev	*edev;

+9 −1
Original line number Diff line number Diff line
@@ -656,6 +656,14 @@ static int bnxt_map_ptp_regs(struct bnxt *bp)
				(ptp->refclk_regs[i] & BNXT_GRC_OFFSET_MASK);
		return 0;
	}
	if (bp->flags & BNXT_FLAG_CHIP_P7) {
		for (i = 0; i < 2; i++) {
			if (reg_arr[i] & BNXT_GRC_BASE_MASK)
				return -EINVAL;
			ptp->refclk_mapped_regs[i] = reg_arr[i];
		}
		return 0;
	}
	return -ENODEV;
}

@@ -1018,7 +1026,7 @@ int bnxt_ptp_init(struct bnxt *bp, bool phc_cfg)
	ptp->stats.ts_lost = 0;
	atomic64_set(&ptp->stats.ts_err, 0);

	if (BNXT_CHIP_P5(bp)) {
	if (bp->flags & BNXT_FLAG_CHIP_P5_PLUS) {
		spin_lock_bh(&ptp->ptp_lock);
		bnxt_refclk_read(bp, NULL, &ptp->current_time);
		WRITE_ONCE(ptp->old_time, ptp->current_time);