Commit 4d942ae3 authored by Evan Quan's avatar Evan Quan Committed by Alex Deucher
Browse files

drm/amd/powerplay: move dpm feature support checking to smu_cmn.c 



Considering it is shared by all ASICs and smu_cmn.c should be
the right place.

Signed-off-by: default avatarEvan Quan <evan.quan@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent d23c3ccc

drivers/gpu/drm/amd/powerplay/amdgpu_smu.c

+0 −21
Original line number Diff line number Diff line
@@ -582,27 +582,6 @@ int smu_feature_set_enabled(struct smu_context *smu, enum smu_feature_mask mask, 
					       enable);

}



int smu_feature_is_supported(struct smu_context *smu, enum smu_feature_mask mask)

{

	struct smu_feature *feature = &smu->smu_feature;

	int feature_id;

	int ret = 0;



	feature_id = smu_cmn_to_asic_specific_index(smu,

						    CMN2ASIC_MAPPING_FEATURE,

						    mask);

	if (feature_id < 0)

		return 0;



	WARN_ON(feature_id > feature->feature_num);



	mutex_lock(&feature->mutex);

	ret = test_bit(feature_id, feature->supported);

	mutex_unlock(&feature->mutex);



	return ret;

}



static int smu_set_funcs(struct amdgpu_device *adev)

{

	struct smu_context *smu = &adev->smu;

drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h

+0 −2
Original line number Diff line number Diff line
@@ -732,8 +732,6 @@ extern int smu_feature_is_enabled(struct smu_context *smu, 
				  enum smu_feature_mask mask);

extern int smu_feature_set_enabled(struct smu_context *smu,

				   enum smu_feature_mask mask, bool enable);

extern int smu_feature_is_supported(struct smu_context *smu,

				    enum smu_feature_mask mask);



int smu_update_table(struct smu_context *smu, enum smu_table_id table_index, int argument,

		     void *table_data, bool drv2smu);

drivers/gpu/drm/amd/powerplay/navi10_ppt.c

+4 −4
Original line number Diff line number Diff line
@@ -1266,8 +1266,8 @@ static int navi10_display_config_changed(struct smu_context *smu) 
	int ret = 0;



	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

	    smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

	    smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,

						  smu->display_config->num_display,

						  NULL);
@@ -1544,13 +1544,13 @@ static int navi10_notify_smc_display_config(struct smu_context *smu) 
	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;

	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;



	if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		clock_req.clock_type = amd_pp_dcef_clock;

		clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;



		ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);

		if (!ret) {

			if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {

			if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {

				ret = smu_send_smc_msg_with_param(smu,

								  SMU_MSG_SetMinDeepSleepDcefclk,

								  min_clocks.dcef_clock_in_sr/100,

drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c

+4 −4
Original line number Diff line number Diff line
@@ -1067,8 +1067,8 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu) 
	int ret = 0;



	if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&

	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

	    smu_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

	    smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&

	    smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {

#if 0

		ret = smu_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,

						  smu->display_config->num_display,
@@ -1347,13 +1347,13 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu) 
	min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;

	min_clocks.memory_clock = smu->display_config->min_mem_set_clock;



	if (smu_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

	if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {

		clock_req.clock_type = amd_pp_dcef_clock;

		clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;



		ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);

		if (!ret) {

			if (smu_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {

			if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {

				ret = smu_send_smc_msg_with_param(smu,

								  SMU_MSG_SetMinDeepSleepDcefclk,

								  min_clocks.dcef_clock_in_sr/100,

drivers/gpu/drm/amd/powerplay/smu_cmn.c

+22 −0
Original line number Diff line number Diff line
@@ -116,3 +116,25 @@ int smu_cmn_to_asic_specific_index(struct smu_context *smu, 
		return -EINVAL;

	}

}



int smu_cmn_feature_is_supported(struct smu_context *smu,

				 enum smu_feature_mask mask)

{

	struct smu_feature *feature = &smu->smu_feature;

	int feature_id;

	int ret = 0;



	feature_id = smu_cmn_to_asic_specific_index(smu,

						    CMN2ASIC_MAPPING_FEATURE,

						    mask);

	if (feature_id < 0)

		return 0;



	WARN_ON(feature_id > feature->feature_num);



	mutex_lock(&feature->mutex);

	ret = test_bit(feature_id, feature->supported);

	mutex_unlock(&feature->mutex);



	return ret;

}