Commit 4db286b0 authored by André Draszik's avatar André Draszik Committed by Krzysztof Kozlowski
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arm64: dts: exynos: gs101: specify empty clocks for remaining pinctrl



The pinctrl instances hsi1, gsactrl, and gsacore need a clock for
register access to work.

Since we haven't implemented the relevant CMUs for the clocks required
by these instances just add empty clocks for now so as to make the DT
pass the validation checks.
Once the clocks are implmented in the gs101 clock driver, these should
be updated then.

Signed-off-by: default avatarAndré Draszik <andre.draszik@linaro.org>
Reviewed-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20240430-samsung-pinctrl-busclock-dts-v2-4-14fc988139dd@linaro.org


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent 8120dc46
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Original line number Diff line number Diff line
@@ -1309,6 +1309,9 @@ usbdrd31_dwc3: usb@0 {
		pinctrl_hsi1: pinctrl@11840000 {
			compatible = "google,gs101-pinctrl";
			reg = <0x11840000 0x00001000>;
			/* TODO: update once support for this CMU exists */
			clocks = <0>;
			clock-names = "pclk";
			interrupts = <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH 0>;
		};

@@ -1422,11 +1425,17 @@ wakeup-interrupt-controller {
		pinctrl_gsactrl: pinctrl@17940000 {
			compatible = "google,gs101-pinctrl";
			reg = <0x17940000 0x00001000>;
			/* TODO: update once support for this CMU exists */
			clocks = <0>;
			clock-names = "pclk";
		};

		pinctrl_gsacore: pinctrl@17a80000 {
			compatible = "google,gs101-pinctrl";
			reg = <0x17a80000 0x00001000>;
			/* TODO: update once support for this CMU exists */
			clocks = <0>;
			clock-names = "pclk";
		};

		cmu_top: clock-controller@1e080000 {