Commit 4dd39dde authored by Linus Torvalds's avatar Linus Torvalds
Browse files

Merge tag 'x86-cpu-2025-07-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip 

Pull x86 cpu update from Ingo Molnar:
 "Add user-space CPUID faulting support for AMD CPUs"

* tag 'x86-cpu-2025-07-29' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/CPU/AMD: Add CPUID faulting support
parents 1645f6ab 5bf2f511

arch/x86/include/asm/cpufeatures.h

+3 −0
Original line number Diff line number Diff line
@@ -458,9 +458,12 @@ 
#define X86_FEATURE_LFENCE_RDTSC	(20*32+ 2) /* LFENCE always serializing / synchronizes RDTSC */

#define X86_FEATURE_VERW_CLEAR		(20*32+ 5) /* The memory form of VERW mitigates TSA */

#define X86_FEATURE_NULL_SEL_CLR_BASE	(20*32+ 6) /* Null Selector Clears Base */



#define X86_FEATURE_AUTOIBRS		(20*32+ 8) /* Automatic IBRS */

#define X86_FEATURE_NO_SMM_CTL_MSR	(20*32+ 9) /* SMM_CTL MSR is not present */



#define X86_FEATURE_GP_ON_USER_CPUID	(20*32+17) /* User CPUID faulting */



#define X86_FEATURE_PREFETCHI		(20*32+20) /* Prefetch Data/Instruction to Cache Level */

#define X86_FEATURE_SBPB		(20*32+27) /* Selective Branch Prediction Barrier */

#define X86_FEATURE_IBPB_BRTYPE		(20*32+28) /* MSR_PRED_CMD[IBPB] flushes all branch type predictions */

arch/x86/include/asm/msr-index.h

+1 −0
Original line number Diff line number Diff line
@@ -831,6 +831,7 @@ 
#define MSR_K7_HWCR_SMMLOCK		BIT_ULL(MSR_K7_HWCR_SMMLOCK_BIT)

#define MSR_K7_HWCR_IRPERF_EN_BIT	30

#define MSR_K7_HWCR_IRPERF_EN		BIT_ULL(MSR_K7_HWCR_IRPERF_EN_BIT)

#define MSR_K7_HWCR_CPUID_USER_DIS_BIT	35

#define MSR_K7_FID_VID_CTL		0xc0010041

#define MSR_K7_FID_VID_STATUS		0xc0010042

#define MSR_K7_HWCR_CPB_DIS_BIT		25

arch/x86/kernel/cpu/amd.c

+3 −1
Original line number Diff line number Diff line
@@ -530,9 +530,11 @@ static void bsp_init_amd(struct cpuinfo_x86 *c) 
	}



	bsp_determine_snp(c);



	tsa_init(c);



	if (cpu_has(c, X86_FEATURE_GP_ON_USER_CPUID))

		setup_force_cpu_cap(X86_FEATURE_CPUID_FAULT);



	return;



warn:

arch/x86/kernel/process.c

+14 −6
Original line number Diff line number Diff line
@@ -334,6 +334,8 @@ DEFINE_PER_CPU(u64, msr_misc_features_shadow); 


static void set_cpuid_faulting(bool on)

{



	if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) {

		u64 msrval;



		msrval = this_cpu_read(msr_misc_features_shadow);
@@ -341,6 +343,12 @@ static void set_cpuid_faulting(bool on) 
		msrval |= (on << MSR_MISC_FEATURES_ENABLES_CPUID_FAULT_BIT);

		this_cpu_write(msr_misc_features_shadow, msrval);

		wrmsrq(MSR_MISC_FEATURES_ENABLES, msrval);

	} else if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD) {

		if (on)

			msr_set_bit(MSR_K7_HWCR, MSR_K7_HWCR_CPUID_USER_DIS_BIT);

		else

			msr_clear_bit(MSR_K7_HWCR, MSR_K7_HWCR_CPUID_USER_DIS_BIT);

	}

}



static void disable_cpuid(void)