Commit 4de36f7b authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson
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ARM: dts: qcom-msm8974: Fix up mdss nodes 



Fix up formatting, move status=disabled to the end where it belongs,
rename DSI PHY label to match newer DTs, use tabs where possible,
unwrap lines where wrapping is not necessary and don't disable mdp,
as MDSS is useless without it.

Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: default avatarBjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20220415115633.575010-6-konrad.dybcio@somainline.org
parent bb167546

arch/arm/boot/dts/qcom-msm8974.dtsi

+34 −43
Original line number Diff line number Diff line
@@ -1459,35 +1459,29 @@ opp-27000000 { 
		};



		mdss: mdss@fd900000 {

			status = "disabled";



			compatible = "qcom,mdss";

			reg = <0xfd900000 0x100>,

			      <0xfd924000 0x1000>;

			reg-names = "mdss_phys",

			            "vbif_phys";

			reg = <0xfd900000 0x100>, <0xfd924000 0x1000>;

			reg-names = "mdss_phys", "vbif_phys";



			power-domains = <&mmcc MDSS_GDSC>;



			clocks = <&mmcc MDSS_AHB_CLK>,

				 <&mmcc MDSS_AXI_CLK>,

				 <&mmcc MDSS_VSYNC_CLK>;

			clock-names = "iface",

			              "bus",

			              "vsync";

			clock-names = "iface", "bus", "vsync";



			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;



			interrupt-controller;

			#interrupt-cells = <1>;



			status = "disabled";



			#address-cells = <1>;

			#size-cells = <1>;

			ranges;



			mdp: mdp@fd900000 {

				status = "disabled";



				compatible = "qcom,mdp5";

				reg = <0xfd900100 0x22000>;

				reg-names = "mdp_phys";
@@ -1499,10 +1493,7 @@ mdp: mdp@fd900000 { 
					 <&mmcc MDSS_AXI_CLK>,

					 <&mmcc MDSS_MDP_CLK>,

					 <&mmcc MDSS_VSYNC_CLK>;

				clock-names = "iface",

				              "bus",

				              "core",

				              "vsync";

				clock-names = "iface", "bus", "core", "vsync";



				interconnects = <&mmssnoc MNOC_MAS_MDP_PORT0 &bimc BIMC_SLV_EBI_CH0>;

				interconnect-names = "mdp0-mem";
@@ -1521,8 +1512,6 @@ mdp5_intf1_out: endpoint { 
			};



			dsi0: dsi@fd922800 {

				status = "disabled";



				compatible = "qcom,mdss-dsi-ctrl";

				reg = <0xfd922800 0x1f8>;

				reg-names = "dsi_ctrl";
@@ -1530,10 +1519,8 @@ dsi0: dsi@fd922800 { 
				interrupt-parent = <&mdss>;

				interrupts = <4>;



				assigned-clocks = <&mmcc BYTE0_CLK_SRC>,

				                  <&mmcc PCLK0_CLK_SRC>;

				assigned-clock-parents = <&dsi_phy0 0>,

				                         <&dsi_phy0 1>;

				assigned-clocks = <&mmcc BYTE0_CLK_SRC>, <&mmcc PCLK0_CLK_SRC>;

				assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;



				clocks = <&mmcc MDSS_MDP_CLK>,

					 <&mmcc MDSS_AHB_CLK>,
@@ -1550,9 +1537,14 @@ dsi0: dsi@fd922800 { 
					      "core",

					      "core_mmss";



				phys = <&dsi_phy0>;

				phys = <&dsi0_phy>;

				phy-names = "dsi-phy";



				status = "disabled";



				#address-cells = <1>;

				#size-cells = <0>;



				ports {

					#address-cells = <1>;

					#size-cells = <0>;
@@ -1572,9 +1564,7 @@ dsi0_out: endpoint { 
				};

			};



			dsi_phy0: dsi-phy@fd922a00 {

				status = "disabled";



			dsi0_phy: dsi-phy@fd922a00 {

				compatible = "qcom,dsi-phy-28nm-hpm";

				reg = <0xfd922a00 0xd4>,

				      <0xfd922b00 0x280>,
@@ -1585,10 +1575,11 @@ dsi_phy0: dsi-phy@fd922a00 { 


				#clock-cells = <1>;

				#phy-cells = <0>;

				qcom,dsi-phy-index = <0>;



				clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>;

				clock-names = "iface", "ref";



				status = "disabled";

			};

		};