Commit 4de4a0f1 authored by Dave Airlie's avatar Dave Airlie
Browse files

Merge tag 'drm-xe-fixes-2024-09-05' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-fixes 



- GSC loading fix (Daniele)
- PCODE mutex fix (Matt)
- Suspend/Resume fixes (Maarten, Imre)
- RPM fixes (Rodrigo)

Signed-off-by: default avatarDave Airlie <airlied@redhat.com>

From: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/ZtmyFvDfFLPbuf6A@intel.com
parents f2064ae3 4bfc9c55

drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h

+4 −4
Original line number Diff line number Diff line
@@ -13,7 +13,7 @@ static inline int 
snb_pcode_write_timeout(struct intel_uncore *uncore, u32 mbox, u32 val,

			int fast_timeout_us, int slow_timeout_ms)

{

	return xe_pcode_write_timeout(__compat_uncore_to_gt(uncore), mbox, val,

	return xe_pcode_write_timeout(__compat_uncore_to_tile(uncore), mbox, val,

				      slow_timeout_ms ?: 1);

}
@@ -21,13 +21,13 @@ static inline int 
snb_pcode_write(struct intel_uncore *uncore, u32 mbox, u32 val)

{



	return xe_pcode_write(__compat_uncore_to_gt(uncore), mbox, val);

	return xe_pcode_write(__compat_uncore_to_tile(uncore), mbox, val);

}



static inline int

snb_pcode_read(struct intel_uncore *uncore, u32 mbox, u32 *val, u32 *val1)

{

	return xe_pcode_read(__compat_uncore_to_gt(uncore), mbox, val, val1);

	return xe_pcode_read(__compat_uncore_to_tile(uncore), mbox, val, val1);

}



static inline int
@@ -35,7 +35,7 @@ skl_pcode_request(struct intel_uncore *uncore, u32 mbox, 
		  u32 request, u32 reply_mask, u32 reply,

		  int timeout_base_ms)

{

	return xe_pcode_request(__compat_uncore_to_gt(uncore), mbox, request, reply_mask, reply,

	return xe_pcode_request(__compat_uncore_to_tile(uncore), mbox, request, reply_mask, reply,

				timeout_base_ms);

}

drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h

+7 −0
Original line number Diff line number Diff line
@@ -17,6 +17,13 @@ static inline struct xe_gt *__compat_uncore_to_gt(struct intel_uncore *uncore) 
	return xe_root_mmio_gt(xe);

}



static inline struct xe_tile *__compat_uncore_to_tile(struct intel_uncore *uncore)

{

	struct xe_device *xe = container_of(uncore, struct xe_device, uncore);



	return xe_device_get_root_tile(xe);

}



static inline u32 intel_uncore_read(struct intel_uncore *uncore,

				    i915_reg_t i915_reg)

{

drivers/gpu/drm/xe/display/xe_display.c

+17 −6
Original line number Diff line number Diff line
@@ -315,8 +315,12 @@ void xe_display_pm_suspend(struct xe_device *xe, bool runtime) 
	 * properly.

	 */

	intel_power_domains_disable(xe);

	if (has_display(xe))

	intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true);

	if (has_display(xe)) {

		drm_kms_helper_poll_disable(&xe->drm);

		if (!runtime)

			intel_display_driver_disable_user_access(xe);

	}



	if (!runtime)

		intel_display_driver_suspend(xe);
@@ -327,12 +331,13 @@ void xe_display_pm_suspend(struct xe_device *xe, bool runtime) 


	intel_hpd_cancel_work(xe);



	if (!runtime && has_display(xe)) {

		intel_display_driver_suspend_access(xe);

		intel_encoder_suspend_all(&xe->display);

	}



	intel_opregion_suspend(xe, s2idle ? PCI_D1 : PCI_D3cold);



	intel_fbdev_set_suspend(&xe->drm, FBINFO_STATE_SUSPENDED, true);



	intel_dmc_suspend(xe);

}
@@ -370,14 +375,20 @@ void xe_display_pm_resume(struct xe_device *xe, bool runtime) 
	intel_display_driver_init_hw(xe);

	intel_hpd_init(xe);



	if (!runtime && has_display(xe))

		intel_display_driver_resume_access(xe);



	/* MST sideband requires HPD interrupts enabled */

	intel_dp_mst_resume(xe);

	if (!runtime)

		intel_display_driver_resume(xe);



	intel_hpd_poll_disable(xe);

	if (has_display(xe))

	if (has_display(xe)) {

		drm_kms_helper_poll_enable(&xe->drm);

		if (!runtime)

			intel_display_driver_enable_user_access(xe);

	}

	intel_hpd_poll_disable(xe);



	intel_opregion_resume(xe);

drivers/gpu/drm/xe/xe_device_types.h

+6 −0
Original line number Diff line number Diff line
@@ -203,6 +203,12 @@ struct xe_tile { 
		} vf;

	} sriov;



	/** @pcode: tile's PCODE */

	struct {

		/** @pcode.lock: protecting tile's PCODE mailbox data */

		struct mutex lock;

	} pcode;



	/** @migrate: Migration helper for vram blits and clearing */

	struct xe_migrate *migrate;

drivers/gpu/drm/xe/xe_gsc.c

+12 −0
Original line number Diff line number Diff line
@@ -519,10 +519,22 @@ int xe_gsc_init_post_hwconfig(struct xe_gsc *gsc) 
void xe_gsc_load_start(struct xe_gsc *gsc)

{

	struct xe_gt *gt = gsc_to_gt(gsc);

	struct xe_device *xe = gt_to_xe(gt);



	if (!xe_uc_fw_is_loadable(&gsc->fw) || !gsc->q)

		return;



	/*

	 * The GSC HW is only reset by driver FLR or D3cold entry. We don't

	 * support the former at runtime, while the latter is only supported on

	 * DGFX, for which we don't support GSC. Therefore, if GSC failed to

	 * load previously there is no need to try again because the HW is

	 * stuck in the error state.

	 */

	xe_assert(xe, !IS_DGFX(xe));

	if (xe_uc_fw_is_in_error_state(&gsc->fw))

		return;



	/* GSC FW survives GT reset and D3Hot */

	if (gsc_fw_is_loaded(gt)) {

		xe_uc_fw_change_status(&gsc->fw, XE_UC_FIRMWARE_TRANSFERRED);