Unverified Commit 4de51e81 authored by Mark Brown's avatar Mark Brown
Browse files

spi: spi-fsl-lpspi: Generic fixes and support for 

Merge series from James Clark <james.clark@linaro.org>:

Various fixes for LPSI along with some refactorings. None of the fixes
are strictly related to S32G, however these changes all originate from
the work to support S32G devices. The only commits that are strictly
related are for the new s32g2 and s32g3 compatible strings.
parents 74462840 431f6c88

CREDITS

+7 −0
Original line number Diff line number Diff line
@@ -3222,6 +3222,10 @@ D: AIC5800 IEEE 1394, RAW I/O on 1394 
D: Starter of Linux1394 effort

S: ask per mail for current address



N: Boris Pismenny

E: borisp@mellanox.com

D: Kernel TLS implementation and offload support.



N: Nicolas Pitre

E: nico@fluxnic.net

D: StrongARM SA1100 support integrator & hacker
@@ -4168,6 +4172,9 @@ S: 1513 Brewster Dr. 
S: Carrollton, TX 75010

S: USA



N: Dave Watson

D: Kernel TLS implementation.



N: Tim Waugh

E: tim@cyberelk.net

D: Co-architect of the parallel-port sharing system

Documentation/admin-guide/hw-vuln/attack_vector_controls.rst

+1 −4
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@@ -215,7 +215,7 @@ Spectre_v2 X X 
Spectre_v2_user                      X                           X            *       (Note 1)

SRBDS                 X              X            X              X

SRSO                  X              X            X              X

SSB                                                                                   (Note 4)

SSB                                  X

TAA                   X              X            X              X            *       (Note 2)

TSA                   X              X            X              X

=============== ============== ============ ============= ============== ============ ========
@@ -229,9 +229,6 @@ Notes: 
   3 --  Disables SMT if cross-thread mitigations are fully enabled, the CPU is

   vulnerable, and STIBP is not supported



   4 --  Speculative store bypass is always enabled by default (no kernel

   mitigation applied) unless overridden with spec_store_bypass_disable option



When an attack-vector is disabled, all mitigations for the vulnerabilities

listed in the above table are disabled, unless mitigation is required for a

different enabled attack-vector or a mitigation is explicitly selected via a

Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml

+0 −1
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@@ -60,7 +60,6 @@ properties: 
          - const: bus

          - const: core

          - const: vsync

          - const: lut

          - const: tbu

          - const: tbu_rt

        # MSM8996 has additional iommu clock

Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml

+5 −0
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@@ -20,6 +20,7 @@ properties: 
      - enum:

          - fsl,imx7ulp-spi

          - fsl,imx8qxp-spi

          - nxp,s32g2-lpspi

      - items:

          - enum:

              - fsl,imx8ulp-spi
@@ -27,6 +28,10 @@ properties: 
              - fsl,imx94-spi

              - fsl,imx95-spi

          - const: fsl,imx7ulp-spi

      - items:

          - const: nxp,s32g3-lpspi

          - const: nxp,s32g2-lpspi



  reg:

    maxItems: 1

Documentation/devicetree/bindings/vendor-prefixes.yaml

+2 −0
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@@ -507,6 +507,8 @@ patternProperties: 
    description: Espressif Systems Co. Ltd.

  "^est,.*":

    description: ESTeem Wireless Modems

  "^eswin,.*":

    description: Beijing ESWIN Technology Group Co. Ltd.

  "^ettus,.*":

    description: NI Ettus Research

  "^eukrea,.*":