Unverified Commit 4e0d439d authored by Maxime Ripard's avatar Maxime Ripard
Browse files

ARM: dts: sunxi: Fix OPP arrays 



Even though it translates to the same thing down to the binary level, we
should have an array of 2 number cells to describe each OPP, which in
turns create a validation warning.

Let's fix this.

Signed-off-by: default avatarMaxime Ripard <maxime@cerno.tech>
Acked-by: default avatarJernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/20210901091852.479202-42-maxime@cerno.tech
parent f7717f28

arch/arm/boot/dts/sun4i-a10-olinuxino-lime.dts

+5 −6
Original line number Diff line number Diff line
@@ -91,12 +91,11 @@ &cpu0 { 
	/*

	 * The A10-Lime is known to be unstable when running at 1008 MHz

	 */

	operating-points = <

	operating-points =

		/* kHz	  uV */

		912000  1350000

		864000  1300000

		624000  1250000

		>;

		<912000	1350000>,

		<864000	1300000>,

		<624000	1250000>;

};



&de {

arch/arm/boot/dts/sun4i-a10.dtsi

+5 −6
Original line number Diff line number Diff line
@@ -115,13 +115,12 @@ cpu0: cpu@0 { 
			reg = <0x0>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

			operating-points =

				/* kHz	  uV */

				1008000 1400000

				912000	1350000

				864000	1300000

				624000	1250000

				>;

				<1008000 1400000>,

				<912000	1350000>,

				<864000	1300000>,

				<624000	1250000>;

			#cooling-cells = <2>;

		};

	};

arch/arm/boot/dts/sun5i-a13.dtsi

+7 −8
Original line number Diff line number Diff line
@@ -102,15 +102,14 @@ &ccu { 


&cpu0 {

	clock-latency = <244144>; /* 8 32k periods */

	operating-points = <

	operating-points =

		/* kHz	  uV */

		1008000 1400000

		912000	1350000

		864000	1300000

		624000	1200000

		576000	1200000

		432000	1200000

		>;

		<1008000 1400000>,

		<912000 1350000>,

		<864000 1300000>,

		<624000 1200000>,

		<576000 1200000>,

		<432000 1200000>;

	#cooling-cells = <2>;

};

arch/arm/boot/dts/sun6i-a31.dtsi

+20 −24
Original line number Diff line number Diff line
@@ -105,13 +105,12 @@ cpu0: cpu@0 { 
			reg = <0>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

			operating-points =

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

				<1008000 1200000>,

				<864000 1200000>,

				<720000 1100000>,

				<480000 1000000>;

			#cooling-cells = <2>;

		};
@@ -121,13 +120,12 @@ cpu1: cpu@1 { 
			reg = <1>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

			operating-points =

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

				<1008000 1200000>,

				<864000 1200000>,

				<720000 1100000>,

				<480000 1000000>;

			#cooling-cells = <2>;

		};
@@ -137,13 +135,12 @@ cpu2: cpu@2 { 
			reg = <2>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

			operating-points =

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

				<1008000 1200000>,

				<864000 1200000>,

				<720000 1100000>,

				<480000 1000000>;

			#cooling-cells = <2>;

		};
@@ -153,13 +150,12 @@ cpu3: cpu@3 { 
			reg = <3>;

			clocks = <&ccu CLK_CPU>;

			clock-latency = <244144>; /* 8 32k periods */

			operating-points = <

			operating-points =

				/* kHz	  uV */

				1008000	1200000

				864000	1200000

				720000	1100000

				480000	1000000

				>;

				<1008000 1200000>,

				<864000 1200000>,

				<720000 1100000>,

				<480000 1000000>;

			#cooling-cells = <2>;

		};

	};

arch/arm/boot/dts/sun7i-a20-bananapi.dts

+8 −9
Original line number Diff line number Diff line
@@ -104,16 +104,15 @@ &codec { 


&cpu0 {

	cpu-supply = <&reg_dcdc2>;

	operating-points = <

	operating-points =

		/* kHz	  uV */

		960000	1400000

		912000	1400000

		864000	1350000

		720000	1250000

		528000	1150000

		312000	1100000

		144000	1050000

		>;

		<960000	1400000>,

		<912000	1400000>,

		<864000	1350000>,

		<720000	1250000>,

		<528000	1150000>,

		<312000	1100000>,

		<144000	1050000>;

};



&de {