Commit 4e14e0fc authored by Rodrigo Siqueira's avatar Rodrigo Siqueira Committed by Alex Deucher
Browse files

drm/amd/display: Move bounding box to FPU folder 



The final part of the DCN32 code that uses FPU is the bounding box code,
and this commit move it to dcn32_fpu.

Tested-by: default avatarDaniel Wheeler <daniel.wheeler@amd.com>
Reviewed-by: default avatarHarry Wentland <Harry.Wentland@amd.com>
Signed-off-by: default avatarRodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent a4f8f294

drivers/gpu/drm/amd/display/dc/dcn32/dcn32_resource.c

+2 −458
Original line number Diff line number Diff line
@@ -1922,29 +1922,6 @@ static struct dc_cap_funcs cap_funcs = { 
	.get_dcc_compression_cap = dcn20_get_dcc_compression_cap

};





static void dcn32_get_optimal_dcfclk_fclk_for_uclk(unsigned int uclk_mts,

		unsigned int *optimal_dcfclk,

		unsigned int *optimal_fclk)

{

	double bw_from_dram, bw_from_dram1, bw_from_dram2;



	bw_from_dram1 = uclk_mts * dcn3_2_soc.num_chans *

		dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_dram_bw_use_normal_percent / 100);

	bw_from_dram2 = uclk_mts * dcn3_2_soc.num_chans *

		dcn3_2_soc.dram_channel_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100);



	bw_from_dram = (bw_from_dram1 < bw_from_dram2) ? bw_from_dram1 : bw_from_dram2;



	if (optimal_fclk)

		*optimal_fclk = bw_from_dram /

		(dcn3_2_soc.fabric_datapath_to_dcn_data_return_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));



	if (optimal_dcfclk)

		*optimal_dcfclk =  bw_from_dram /

		(dcn3_2_soc.return_bus_width_bytes * (dcn3_2_soc.max_avg_sdp_bw_use_normal_percent / 100));

}



void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context,

				display_e2e_pipe_params_st *pipes,

				int pipe_cnt,
@@ -1955,446 +1932,13 @@ void dcn32_calculate_wm_and_dlg(struct dc *dc, struct dc_state *context, 
    DC_FP_END();

}



static void remove_entry_from_table_at_index(struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries,

		unsigned int index)

{

	int i;



	if (*num_entries == 0)

		return;



	for (i = index; i < *num_entries - 1; i++) {

		table[i] = table[i + 1];

	}

	memset(&table[--(*num_entries)], 0, sizeof(struct _vcs_dpi_voltage_scaling_st));

}



static int build_synthetic_soc_states(struct clk_bw_params *bw_params,

		struct _vcs_dpi_voltage_scaling_st *table, unsigned int *num_entries)

static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	int i, j;

	struct _vcs_dpi_voltage_scaling_st entry = {0};



	unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,

			max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0, max_uclk_mhz = 0;



	unsigned int min_dcfclk_mhz = 199, min_fclk_mhz = 299;



	static const unsigned int num_dcfclk_stas = 5;

	unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};



	unsigned int num_uclk_dpms = 0;

	unsigned int num_fclk_dpms = 0;

	unsigned int num_dcfclk_dpms = 0;



	for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

		if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)

			max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;

		if (bw_params->clk_table.entries[i].fclk_mhz > max_fclk_mhz)

			max_fclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;

		if (bw_params->clk_table.entries[i].memclk_mhz > max_uclk_mhz)

			max_uclk_mhz = bw_params->clk_table.entries[i].memclk_mhz;

		if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)

			max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;

		if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)

			max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;

		if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)

			max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;

		if (bw_params->clk_table.entries[i].dtbclk_mhz > max_dtbclk_mhz)

			max_dtbclk_mhz = bw_params->clk_table.entries[i].dtbclk_mhz;



		if (bw_params->clk_table.entries[i].memclk_mhz > 0)

			num_uclk_dpms++;

		if (bw_params->clk_table.entries[i].fclk_mhz > 0)

			num_fclk_dpms++;

		if (bw_params->clk_table.entries[i].dcfclk_mhz > 0)

			num_dcfclk_dpms++;

	}



	if (!max_dcfclk_mhz || !max_dispclk_mhz || !max_dtbclk_mhz)

		return -1;



	if (max_dppclk_mhz == 0)

		max_dppclk_mhz = max_dispclk_mhz;



	if (max_fclk_mhz == 0)

		max_fclk_mhz = max_dcfclk_mhz * dcn3_2_soc.pct_ideal_sdp_bw_after_urgent / dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;



	if (max_phyclk_mhz == 0)

		max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;



	*num_entries = 0;

	entry.dispclk_mhz = max_dispclk_mhz;

	entry.dscclk_mhz = max_dispclk_mhz / 3;

	entry.dppclk_mhz = max_dppclk_mhz;

	entry.dtbclk_mhz = max_dtbclk_mhz;

	entry.phyclk_mhz = max_phyclk_mhz;

	entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;

	entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;



	// Insert all the DCFCLK STAs

	for (i = 0; i < num_dcfclk_stas; i++) {

		entry.dcfclk_mhz = dcfclk_sta_targets[i];

		entry.fabricclk_mhz = 0;

		entry.dram_speed_mts = 0;



	DC_FP_START();

		insert_entry_into_table_sorted(table, num_entries, &entry);

	dcn32_update_bw_bounding_box_fpu(dc, bw_params);

	DC_FP_END();

}



	// Insert the max DCFCLK

	entry.dcfclk_mhz = max_dcfclk_mhz;

	entry.fabricclk_mhz = 0;

	entry.dram_speed_mts = 0;



	DC_FP_START();

	insert_entry_into_table_sorted(table, num_entries, &entry);

	DC_FP_END();



	// Insert the UCLK DPMS

	for (i = 0; i < num_uclk_dpms; i++) {

		entry.dcfclk_mhz = 0;

		entry.fabricclk_mhz = 0;

		entry.dram_speed_mts = bw_params->clk_table.entries[i].memclk_mhz * 16;



		DC_FP_START();

		insert_entry_into_table_sorted(table, num_entries, &entry);

		DC_FP_END();

	}



	// If FCLK is coarse grained, insert individual DPMs.

	if (num_fclk_dpms > 2) {

		for (i = 0; i < num_fclk_dpms; i++) {

			entry.dcfclk_mhz = 0;

			entry.fabricclk_mhz = bw_params->clk_table.entries[i].fclk_mhz;

			entry.dram_speed_mts = 0;



			DC_FP_START();

			insert_entry_into_table_sorted(table, num_entries, &entry);

			DC_FP_END();

		}

	}

	// If FCLK fine grained, only insert max

	else {

		entry.dcfclk_mhz = 0;

		entry.fabricclk_mhz = max_fclk_mhz;

		entry.dram_speed_mts = 0;



		DC_FP_START();

		insert_entry_into_table_sorted(table, num_entries, &entry);

		DC_FP_END();

	}



	// At this point, the table contains all "points of interest" based on

	// DPMs from PMFW, and STAs.  Table is sorted by BW, and all clock

	// ratios (by derate, are exact).



	// Remove states that require higher clocks than are supported

	for (i = *num_entries - 1; i >= 0 ; i--) {

		if (table[i].dcfclk_mhz > max_dcfclk_mhz ||

				table[i].fabricclk_mhz > max_fclk_mhz ||

				table[i].dram_speed_mts > max_uclk_mhz * 16)

			remove_entry_from_table_at_index(table, num_entries, i);

	}



	// At this point, the table only contains supported points of interest

	// it could be used as is, but some states may be redundant due to

	// coarse grained nature of some clocks, so we want to round up to

	// coarse grained DPMs and remove duplicates.



	// Round up UCLKs

	for (i = *num_entries - 1; i >= 0 ; i--) {

		for (j = 0; j < num_uclk_dpms; j++) {

			if (bw_params->clk_table.entries[j].memclk_mhz * 16 >= table[i].dram_speed_mts) {

				table[i].dram_speed_mts = bw_params->clk_table.entries[j].memclk_mhz * 16;

				break;

			}

		}

	}



	// If FCLK is coarse grained, round up to next DPMs

	if (num_fclk_dpms > 2) {

		for (i = *num_entries - 1; i >= 0 ; i--) {

			for (j = 0; j < num_fclk_dpms; j++) {

				if (bw_params->clk_table.entries[j].fclk_mhz >= table[i].fabricclk_mhz) {

					table[i].fabricclk_mhz = bw_params->clk_table.entries[j].fclk_mhz;

					break;

				}

			}

		}

	}

	// Otherwise, round up to minimum.

	else {

		for (i = *num_entries - 1; i >= 0 ; i--) {

			if (table[i].fabricclk_mhz < min_fclk_mhz) {

				table[i].fabricclk_mhz = min_fclk_mhz;

				break;

			}

		}

	}



	// Round DCFCLKs up to minimum

	for (i = *num_entries - 1; i >= 0 ; i--) {

		if (table[i].dcfclk_mhz < min_dcfclk_mhz) {

			table[i].dcfclk_mhz = min_dcfclk_mhz;

			break;

		}

	}



	// Remove duplicate states, note duplicate states are always neighbouring since table is sorted.

	i = 0;

	while (i < *num_entries - 1) {

		if (table[i].dcfclk_mhz == table[i + 1].dcfclk_mhz &&

				table[i].fabricclk_mhz == table[i + 1].fabricclk_mhz &&

				table[i].dram_speed_mts == table[i + 1].dram_speed_mts)

			remove_entry_from_table_at_index(table, num_entries, i + 1);

		else

			i++;

	}



	// Fix up the state indicies

	for (i = *num_entries - 1; i >= 0 ; i--) {

		table[i].state = i;

	}



	return 0;

}



/* dcn32_update_bw_bounding_box

 * This would override some dcn3_2 ip_or_soc initial parameters hardcoded from spreadsheet

 * with actual values as per dGPU SKU:

 * -with passed few options from dc->config

 * -with dentist_vco_frequency from Clk Mgr (currently hardcoded, but might need to get it from PM FW)

 * -with passed latency values (passed in ns units) in dc-> bb override for debugging purposes

 * -with passed latencies from VBIOS (in 100_ns units) if available for certain dGPU SKU

 * -with number of DRAM channels from VBIOS (which differ for certain dGPU SKU of the same ASIC)

 * -clocks levels with passed clk_table entries from Clk Mgr as reported by PM FW for different

 *  clocks (which might differ for certain dGPU SKU of the same ASIC)

 */

static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw_params)

{

	if (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) {



		/* Overrides from dc->config options */

		dcn3_2_ip.clamp_min_dcfclk = dc->config.clamp_min_dcfclk;



		/* Override from passed dc->bb_overrides if available*/

		if ((int)(dcn3_2_soc.sr_exit_time_us * 1000) != dc->bb_overrides.sr_exit_time_ns

				&& dc->bb_overrides.sr_exit_time_ns) {

			dcn3_2_soc.sr_exit_time_us = dc->bb_overrides.sr_exit_time_ns / 1000.0;

		}



		if ((int)(dcn3_2_soc.sr_enter_plus_exit_time_us * 1000)

				!= dc->bb_overrides.sr_enter_plus_exit_time_ns

				&& dc->bb_overrides.sr_enter_plus_exit_time_ns) {

			dcn3_2_soc.sr_enter_plus_exit_time_us =

				dc->bb_overrides.sr_enter_plus_exit_time_ns / 1000.0;

		}



		if ((int)(dcn3_2_soc.urgent_latency_us * 1000) != dc->bb_overrides.urgent_latency_ns

			&& dc->bb_overrides.urgent_latency_ns) {

			dcn3_2_soc.urgent_latency_us = dc->bb_overrides.urgent_latency_ns / 1000.0;

		}



		if ((int)(dcn3_2_soc.dram_clock_change_latency_us * 1000)

				!= dc->bb_overrides.dram_clock_change_latency_ns

				&& dc->bb_overrides.dram_clock_change_latency_ns) {

			dcn3_2_soc.dram_clock_change_latency_us =

				dc->bb_overrides.dram_clock_change_latency_ns / 1000.0;

		}



		if ((int)(dcn3_2_soc.dummy_pstate_latency_us * 1000)

				!= dc->bb_overrides.dummy_clock_change_latency_ns

				&& dc->bb_overrides.dummy_clock_change_latency_ns) {

			dcn3_2_soc.dummy_pstate_latency_us =

				dc->bb_overrides.dummy_clock_change_latency_ns / 1000.0;

		}



		/* Override from VBIOS if VBIOS bb_info available */

		if (dc->ctx->dc_bios->funcs->get_soc_bb_info) {

			struct bp_soc_bb_info bb_info = {0};



			if (dc->ctx->dc_bios->funcs->get_soc_bb_info(dc->ctx->dc_bios, &bb_info) == BP_RESULT_OK) {

				if (bb_info.dram_clock_change_latency_100ns > 0)

					dcn3_2_soc.dram_clock_change_latency_us = bb_info.dram_clock_change_latency_100ns * 10;



			if (bb_info.dram_sr_enter_exit_latency_100ns > 0)

				dcn3_2_soc.sr_enter_plus_exit_time_us = bb_info.dram_sr_enter_exit_latency_100ns * 10;



			if (bb_info.dram_sr_exit_latency_100ns > 0)

				dcn3_2_soc.sr_exit_time_us = bb_info.dram_sr_exit_latency_100ns * 10;

			}

		}



		/* Override from VBIOS for num_chan */

		if (dc->ctx->dc_bios->vram_info.num_chans)

			dcn3_2_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans;



		if (dc->ctx->dc_bios->vram_info.dram_channel_width_bytes)

			dcn3_2_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes;



	}



	/* Override dispclk_dppclk_vco_speed_mhz from Clk Mgr */

	dcn3_2_soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;

	dc->dml.soc.dispclk_dppclk_vco_speed_mhz = dc->clk_mgr->dentist_vco_freq_khz / 1000.0;



	/* Overrides Clock levelsfrom CLK Mgr table entries as reported by PM FW */

	if ((!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment)) && (bw_params->clk_table.entries[0].memclk_mhz)) {

		if (dc->debug.use_legacy_soc_bb_mechanism) {

			unsigned int i = 0, j = 0, num_states = 0;



			unsigned int dcfclk_mhz[DC__VOLTAGE_STATES] = {0};

			unsigned int dram_speed_mts[DC__VOLTAGE_STATES] = {0};

			unsigned int optimal_uclk_for_dcfclk_sta_targets[DC__VOLTAGE_STATES] = {0};

			unsigned int optimal_dcfclk_for_uclk[DC__VOLTAGE_STATES] = {0};

			unsigned int min_dcfclk = UINT_MAX;

			/* Set 199 as first value in STA target array to have a minimum DCFCLK value.

			 * For DCN32 we set min to 199 so minimum FCLK DPM0 (300Mhz can be achieved) */

			unsigned int dcfclk_sta_targets[DC__VOLTAGE_STATES] = {199, 615, 906, 1324, 1564};

			unsigned int num_dcfclk_sta_targets = 4, num_uclk_states = 0;

			unsigned int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0, max_phyclk_mhz = 0;



			for (i = 0; i < MAX_NUM_DPM_LVL; i++) {

				if (bw_params->clk_table.entries[i].dcfclk_mhz > max_dcfclk_mhz)

					max_dcfclk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;

				if (bw_params->clk_table.entries[i].dcfclk_mhz != 0 &&

						bw_params->clk_table.entries[i].dcfclk_mhz < min_dcfclk)

					min_dcfclk = bw_params->clk_table.entries[i].dcfclk_mhz;

				if (bw_params->clk_table.entries[i].dispclk_mhz > max_dispclk_mhz)

					max_dispclk_mhz = bw_params->clk_table.entries[i].dispclk_mhz;

				if (bw_params->clk_table.entries[i].dppclk_mhz > max_dppclk_mhz)

					max_dppclk_mhz = bw_params->clk_table.entries[i].dppclk_mhz;

				if (bw_params->clk_table.entries[i].phyclk_mhz > max_phyclk_mhz)

					max_phyclk_mhz = bw_params->clk_table.entries[i].phyclk_mhz;

			}

			if (min_dcfclk > dcfclk_sta_targets[0])

				dcfclk_sta_targets[0] = min_dcfclk;

			if (!max_dcfclk_mhz)

				max_dcfclk_mhz = dcn3_2_soc.clock_limits[0].dcfclk_mhz;

			if (!max_dispclk_mhz)

				max_dispclk_mhz = dcn3_2_soc.clock_limits[0].dispclk_mhz;

			if (!max_dppclk_mhz)

				max_dppclk_mhz = dcn3_2_soc.clock_limits[0].dppclk_mhz;

			if (!max_phyclk_mhz)

				max_phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;



			if (max_dcfclk_mhz > dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {

				// If max DCFCLK is greater than the max DCFCLK STA target, insert into the DCFCLK STA target array

				dcfclk_sta_targets[num_dcfclk_sta_targets] = max_dcfclk_mhz;

				num_dcfclk_sta_targets++;

			} else if (max_dcfclk_mhz < dcfclk_sta_targets[num_dcfclk_sta_targets-1]) {

				// If max DCFCLK is less than the max DCFCLK STA target, cap values and remove duplicates

				for (i = 0; i < num_dcfclk_sta_targets; i++) {

					if (dcfclk_sta_targets[i] > max_dcfclk_mhz) {

						dcfclk_sta_targets[i] = max_dcfclk_mhz;

						break;

					}

				}

				// Update size of array since we "removed" duplicates

				num_dcfclk_sta_targets = i + 1;

			}



			num_uclk_states = bw_params->clk_table.num_entries;



			// Calculate optimal dcfclk for each uclk

			for (i = 0; i < num_uclk_states; i++) {

				dcn32_get_optimal_dcfclk_fclk_for_uclk(bw_params->clk_table.entries[i].memclk_mhz * 16,

						&optimal_dcfclk_for_uclk[i], NULL);

				if (optimal_dcfclk_for_uclk[i] < bw_params->clk_table.entries[0].dcfclk_mhz) {

					optimal_dcfclk_for_uclk[i] = bw_params->clk_table.entries[0].dcfclk_mhz;

				}

			}



			// Calculate optimal uclk for each dcfclk sta target

			for (i = 0; i < num_dcfclk_sta_targets; i++) {

				for (j = 0; j < num_uclk_states; j++) {

					if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j]) {

						optimal_uclk_for_dcfclk_sta_targets[i] =

								bw_params->clk_table.entries[j].memclk_mhz * 16;

						break;

					}

				}

			}



			i = 0;

			j = 0;

			// create the final dcfclk and uclk table

			while (i < num_dcfclk_sta_targets && j < num_uclk_states && num_states < DC__VOLTAGE_STATES) {

				if (dcfclk_sta_targets[i] < optimal_dcfclk_for_uclk[j] && i < num_dcfclk_sta_targets) {

					dcfclk_mhz[num_states] = dcfclk_sta_targets[i];

					dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];

				} else {

					if (j < num_uclk_states && optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {

						dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];

						dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;

					} else {

						j = num_uclk_states;

					}

				}

			}



			while (i < num_dcfclk_sta_targets && num_states < DC__VOLTAGE_STATES) {

				dcfclk_mhz[num_states] = dcfclk_sta_targets[i];

				dram_speed_mts[num_states++] = optimal_uclk_for_dcfclk_sta_targets[i++];

			}



			while (j < num_uclk_states && num_states < DC__VOLTAGE_STATES &&

					optimal_dcfclk_for_uclk[j] <= max_dcfclk_mhz) {

				dcfclk_mhz[num_states] = optimal_dcfclk_for_uclk[j];

				dram_speed_mts[num_states++] = bw_params->clk_table.entries[j++].memclk_mhz * 16;

			}



			dcn3_2_soc.num_states = num_states;

			for (i = 0; i < dcn3_2_soc.num_states; i++) {

				dcn3_2_soc.clock_limits[i].state = i;

				dcn3_2_soc.clock_limits[i].dcfclk_mhz = dcfclk_mhz[i];

				dcn3_2_soc.clock_limits[i].fabricclk_mhz = dcfclk_mhz[i];



				/* Fill all states with max values of all these clocks */

				dcn3_2_soc.clock_limits[i].dispclk_mhz = max_dispclk_mhz;

				dcn3_2_soc.clock_limits[i].dppclk_mhz  = max_dppclk_mhz;

				dcn3_2_soc.clock_limits[i].phyclk_mhz  = max_phyclk_mhz;

				dcn3_2_soc.clock_limits[i].dscclk_mhz  = max_dispclk_mhz / 3;



				/* Populate from bw_params for DTBCLK, SOCCLK */

				if (i > 0) {

					if (!bw_params->clk_table.entries[i].dtbclk_mhz) {

						dcn3_2_soc.clock_limits[i].dtbclk_mhz  = dcn3_2_soc.clock_limits[i-1].dtbclk_mhz;

					} else {

						dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;

					}

				} else if (bw_params->clk_table.entries[i].dtbclk_mhz) {

					dcn3_2_soc.clock_limits[i].dtbclk_mhz  = bw_params->clk_table.entries[i].dtbclk_mhz;

				}



				if (!bw_params->clk_table.entries[i].socclk_mhz && i > 0)

					dcn3_2_soc.clock_limits[i].socclk_mhz = dcn3_2_soc.clock_limits[i-1].socclk_mhz;

				else

					dcn3_2_soc.clock_limits[i].socclk_mhz = bw_params->clk_table.entries[i].socclk_mhz;



				if (!dram_speed_mts[i] && i > 0)

					dcn3_2_soc.clock_limits[i].dram_speed_mts = dcn3_2_soc.clock_limits[i-1].dram_speed_mts;

				else

					dcn3_2_soc.clock_limits[i].dram_speed_mts = dram_speed_mts[i];



				/* These clocks cannot come from bw_params, always fill from dcn3_2_soc[0] */

				/* PHYCLK_D18, PHYCLK_D32 */

				dcn3_2_soc.clock_limits[i].phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;

				dcn3_2_soc.clock_limits[i].phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;

			}

		} else {

			build_synthetic_soc_states(bw_params, dcn3_2_soc.clock_limits, &dcn3_2_soc.num_states);

		}



		/* Re-init DML with updated bb */

		dml_init_instance(&dc->dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);

		if (dc->current_state)

			dml_init_instance(&dc->current_state->bw_ctx.dml, &dcn3_2_soc, &dcn3_2_ip, DML_PROJECT_DCN32);

	}

}



static struct resource_funcs dcn32_res_pool_funcs = {

	.destroy = dcn32_destroy_resource_pool,

	.link_enc_create = dcn32_link_encoder_create,

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c

+470 −0

File changed.

Preview size limit exceeded, changes collapsed.

drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.h

+2 −0
Original line number Diff line number Diff line
@@ -69,4 +69,6 @@ void dcn32_calculate_wm_and_dlg_fpu(struct dc *dc, struct dc_state *context, 
				int pipe_cnt,

				int vlevel);



void dcn32_update_bw_bounding_box_fpu(struct dc *dc, struct clk_bw_params *bw_params);



#endif