Commit 4e1b09d9 authored by Suravee Suthikulpanit's avatar Suravee Suthikulpanit Committed by Joerg Roedel
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iommu/amd: Refactor persistent DTE bits programming into amd_iommu_make_clear_dte() 



To help avoid duplicate logic when programing DTE for nested translation.

Note that this commit changes behavior of when the IOMMU driver is
switching domain during attach and the blocking domain, where DTE bit
fields for interrupt pass-through (i.e. Lint0, Lint1, NMI, INIT, ExtInt)
and System management message could be affected. These DTE bits are
specified in the IVRS table for specific devices, and should be persistent.

Suggested-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Reviewed-by: default avatarJason Gunthorpe <jgg@nvidia.com>
Reviewed-by: default avatarNicolin Chen <nicolinc@nvidia.com>
Signed-off-by: default avatarSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: default avatarJoerg Roedel <joerg.roedel@amd.com>
parent 757d2b1f

drivers/iommu/amd/amd_iommu.h

+13 −0
Original line number Diff line number Diff line
@@ -197,9 +197,22 @@ void amd_iommu_update_dte(struct amd_iommu *iommu, 
static inline void

amd_iommu_make_clear_dte(struct iommu_dev_data *dev_data, struct dev_table_entry *new)

{

	struct dev_table_entry *initial_dte;

	struct amd_iommu *iommu = get_amd_iommu_from_dev(dev_data->dev);



	/* All existing DTE must have V bit set */

	new->data128[0] = DTE_FLAG_V;

	new->data128[1] = 0;



	/*

	 * Restore cached persistent DTE bits, which can be set by information

	 * in IVRS table. See set_dev_entry_from_acpi().

	 */

	initial_dte = amd_iommu_get_ivhd_dte_flags(iommu->pci_seg->id, dev_data->devid);

	if (initial_dte) {

		new->data128[0] |= initial_dte->data128[0];

		new->data128[1] |= initial_dte->data128[1];

	}

}



/* NESTED */

drivers/iommu/amd/iommu.c

+0 −11
Original line number Diff line number Diff line
@@ -2110,7 +2110,6 @@ static void set_dte_entry(struct amd_iommu *iommu, 
{

	u16 domid;

	u32 old_domid;

	struct dev_table_entry *initial_dte;

	struct dev_table_entry new = {};

	struct protection_domain *domain = dev_data->domain;

	struct gcr3_tbl_info *gcr3_info = &dev_data->gcr3_info;
@@ -2168,16 +2167,6 @@ static void set_dte_entry(struct amd_iommu *iommu, 
	old_domid = READ_ONCE(dte->data[1]) & DTE_DOMID_MASK;

	new.data[1] |= domid;



	/*

	 * Restore cached persistent DTE bits, which can be set by information

	 * in IVRS table. See set_dev_entry_from_acpi().

	 */

	initial_dte = amd_iommu_get_ivhd_dte_flags(iommu->pci_seg->id, dev_data->devid);

	if (initial_dte) {

		new.data128[0] |= initial_dte->data128[0];

		new.data128[1] |= initial_dte->data128[1];

	}



	set_dte_gcr3_table(iommu, dev_data, &new);



	amd_iommu_update_dte(iommu, dev_data, &new);