Commit 4e343c11 authored by Jianbo Liu's avatar Jianbo Liu Committed by Paolo Abeni
Browse files

net/mlx5e: Support FEC settings for 200G per lane link modes 



Add support to show and config FEC by ethtool for 200G/lane link
modes. The RS encoding setting is mapped, and can be overridden to
FEC_RS_544_514_INTERLEAVED_QUAD for these modes.

Signed-off-by: default avatarJianbo Liu <jianbol@nvidia.com>
Reviewed-by: default avatarShahar Shitrit <shshitrit@nvidia.com>
Signed-off-by: default avatarTariq Toukan <tariqt@nvidia.com>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent ee0a4fc3

drivers/net/ethernet/mellanox/mlx5/core/en/port.c

+54 −10
Original line number Diff line number Diff line
@@ -296,11 +296,16 @@ enum mlx5e_fec_supported_link_mode { 
	MLX5E_FEC_SUPPORTED_LINK_MODE_200G_2X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_400G_4X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X,

	MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X,

	MLX5E_MAX_FEC_SUPPORTED_LINK_MODE,

};



#define MLX5E_FEC_FIRST_50G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_50G_1X

#define MLX5E_FEC_FIRST_100G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_100G_1X

#define MLX5E_FEC_FIRST_200G_PER_LANE_MODE MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X



#define MLX5E_FEC_OVERRIDE_ADMIN_POLICY(buf, policy, write, link)			\

	do {										\
@@ -320,8 +325,10 @@ static bool mlx5e_is_fec_supported_link_mode(struct mlx5_core_dev *dev, 
	return link_mode < MLX5E_FEC_FIRST_50G_PER_LANE_MODE ||

	       (link_mode < MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&

		MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm)) ||

	       (link_mode >= MLX5E_FEC_FIRST_100G_PER_LANE_MODE &&

		MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm));

	       (link_mode < MLX5E_FEC_FIRST_200G_PER_LANE_MODE &&

		MLX5_CAP_PCAM_FEATURE(dev, fec_100G_per_lane_in_pplm)) ||

	       (link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE &&

		MLX5_CAP_PCAM_FEATURE(dev, fec_200G_per_lane_in_pplm));

}



/* get/set FEC admin field for a given speed */
@@ -368,6 +375,18 @@ static int mlx5e_fec_admin_field(u32 *pplm, u16 *fec_policy, bool write, 
	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_8x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 200g_1x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 400g_2x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 800g_4x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X:

		MLX5E_FEC_OVERRIDE_ADMIN_POLICY(pplm, *fec_policy, write, 1600g_8x);

		break;

	default:

		return -EINVAL;

	}
@@ -421,6 +440,18 @@ static int mlx5e_get_fec_cap_field(u32 *pplm, u16 *fec_cap, 
	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_8X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_8x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_200G_1X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 200g_1x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_400G_2X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 400g_2x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_800G_4X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 800g_4x);

		break;

	case MLX5E_FEC_SUPPORTED_LINK_MODE_1600G_8X:

		*fec_cap = MLX5E_GET_FEC_OVERRIDE_CAP(pplm, 1600g_8x);

		break;

	default:

		return -EINVAL;

	}
@@ -494,6 +525,26 @@ int mlx5e_get_fec_mode(struct mlx5_core_dev *dev, u32 *fec_mode_active, 
	return 0;

}



static u16 mlx5e_remap_fec_conf_mode(enum mlx5e_fec_supported_link_mode link_mode,

				     u16 conf_fec)

{

	/* RS fec in ethtool is originally mapped to MLX5E_FEC_RS_528_514.

	 * For link modes up to 25G per lane, the value is kept.

	 * For 50G or 100G per lane, it's remapped to MLX5E_FEC_RS_544_514.

	 * For 200G per lane, remapped to MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD.

	 */

	if (conf_fec != BIT(MLX5E_FEC_RS_528_514))

		return conf_fec;



	if (link_mode >= MLX5E_FEC_FIRST_200G_PER_LANE_MODE)

		return BIT(MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD);



	if (link_mode >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE)

		return BIT(MLX5E_FEC_RS_544_514);



	return conf_fec;

}



int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy)

{

	bool fec_50g_per_lane = MLX5_CAP_PCAM_FEATURE(dev, fec_50G_per_lane_in_pplm);
@@ -530,14 +581,7 @@ int mlx5e_set_fec_mode(struct mlx5_core_dev *dev, u16 fec_policy) 
		if (!mlx5e_is_fec_supported_link_mode(dev, i))

			break;



		/* RS fec in ethtool is mapped to MLX5E_FEC_RS_528_514

		 * to link modes up to 25G per lane and to

		 * MLX5E_FEC_RS_544_514 in the new link modes based on

		 * 50G or 100G per lane

		 */

		if (conf_fec == (1 << MLX5E_FEC_RS_528_514) &&

		    i >= MLX5E_FEC_FIRST_50G_PER_LANE_MODE)

			conf_fec = (1 << MLX5E_FEC_RS_544_514);

		conf_fec = mlx5e_remap_fec_conf_mode(i, conf_fec);



		mlx5e_get_fec_cap_field(out, &fec_caps, i);

drivers/net/ethernet/mellanox/mlx5/core/en/port.h

+1 −0
Original line number Diff line number Diff line
@@ -61,6 +61,7 @@ enum { 
	MLX5E_FEC_NOFEC,

	MLX5E_FEC_FIRECODE,

	MLX5E_FEC_RS_528_514,

	MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD = 4,

	MLX5E_FEC_RS_544_514 = 7,

	MLX5E_FEC_LLRS_272_257_1 = 9,

};

drivers/net/ethernet/mellanox/mlx5/core/en_ethtool.c

+1 −0
Original line number Diff line number Diff line
@@ -952,6 +952,7 @@ static const u32 pplm_fec_2_ethtool[] = { 
	[MLX5E_FEC_RS_528_514] = ETHTOOL_FEC_RS,

	[MLX5E_FEC_RS_544_514] = ETHTOOL_FEC_RS,

	[MLX5E_FEC_LLRS_272_257_1] = ETHTOOL_FEC_LLRS,

	[MLX5E_FEC_RS_544_514_INTERLEAVED_QUAD] = ETHTOOL_FEC_RS,

};



static u32 pplm2ethtool_fec(u_long fec_mode, unsigned long size)