Commit 4e39e5b8 authored by David Virag's avatar David Virag Committed by Krzysztof Kozlowski
Browse files

clk: samsung: clk-pll: Add support for pll_1418x 



pll1418x is used in Exynos7885 SoC for USB PHY clock.
Operation-wise it is very similar to pll0822x, except that MDIV is only
9 bits wide instead of 10, and we use the CON1 register in the PLL
macro's "con" parameter instead of CON3 like this:

	PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
	    PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
	    pll_usb_rate_table),

Technically the PLL should work fine with pll0822x code if the PLL
tables are correct, but it's more "correct" to actually update the mask.

Signed-off-by: default avatarDavid Virag <virag.david003@gmail.com>
Link: https://lore.kernel.org/r/20240816175034.769628-2-virag.david003@gmail.com


Signed-off-by: default avatarKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
parent ae073894

drivers/clk/samsung/clk-pll.c

+15 −3
Original line number Diff line number Diff line
@@ -430,6 +430,9 @@ static const struct clk_ops samsung_pll36xx_clk_min_ops = { 
#define PLL0822X_LOCK_STAT_SHIFT	(29)

#define PLL0822X_ENABLE_SHIFT		(31)



/* PLL1418x is similar to PLL0822x, except that MDIV is one bit smaller */

#define PLL1418X_MDIV_MASK		(0x1FF)



static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw,

						  unsigned long parent_rate)

{
@@ -438,7 +441,10 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, 
	u64 fvco = parent_rate;



	pll_con3 = readl_relaxed(pll->con_reg);

	if (pll->type != pll_1418x)

		mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL0822X_MDIV_MASK;

	else

		mdiv = (pll_con3 >> PLL0822X_MDIV_SHIFT) & PLL1418X_MDIV_MASK;

	pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK;

	sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK;
@@ -456,7 +462,12 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, 
{

	const struct samsung_pll_rate_table *rate;

	struct samsung_clk_pll *pll = to_clk_pll(hw);

	u32 pll_con3;

	u32 mdiv_mask, pll_con3;



	if (pll->type != pll_1418x)

		mdiv_mask = PLL0822X_MDIV_MASK;

	else

		mdiv_mask = PLL1418X_MDIV_MASK;



	/* Get required rate settings from table */

	rate = samsung_get_pll_settings(pll, drate);
@@ -468,7 +479,7 @@ static int samsung_pll0822x_set_rate(struct clk_hw *hw, unsigned long drate, 


	/* Change PLL PMS values */

	pll_con3 = readl_relaxed(pll->con_reg);

	pll_con3 &= ~((PLL0822X_MDIV_MASK << PLL0822X_MDIV_SHIFT) |

	pll_con3 &= ~((mdiv_mask << PLL0822X_MDIV_SHIFT) |

			(PLL0822X_PDIV_MASK << PLL0822X_PDIV_SHIFT) |

			(PLL0822X_SDIV_MASK << PLL0822X_SDIV_SHIFT));

	pll_con3 |= (rate->mdiv << PLL0822X_MDIV_SHIFT) |
@@ -1317,6 +1328,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, 
			init.ops = &samsung_pll35xx_clk_ops;

		break;

	case pll_1417x:

	case pll_1418x:

	case pll_0818x:

	case pll_0822x:

	case pll_0516x:

drivers/clk/samsung/clk-pll.h

+1 −0
Original line number Diff line number Diff line
@@ -30,6 +30,7 @@ enum samsung_pll_type { 
	pll_2650x,

	pll_2650xx,

	pll_1417x,

	pll_1418x,

	pll_1450x,

	pll_1451x,

	pll_1452x,