Commit 4e412312 authored by Jakub Kicinski's avatar Jakub Kicinski
Browse files
Tony Nguyen says:

====================
Intel Wired LAN Driver Updates 2025-02-10 (ice, igc, e1000e)

For ice:

Karol, Jake, and Michal add PTP support for E830 devices. Karol
refactors and cleans up PTP code. Jake allows for a common
cross-timestamp implementation to be shared for all devices and
Michal adds E830 support.

Mateusz cleans up initial Flow Director rule creation to loop rather
than duplicate repeated similar calls.

For igc:

Siang adjust calls to remove need for close and open calls on loading
XDP program.

For e1000e:

Gerhard Engleder batches register writes for writing multicast table
on real-time kernels.

* '100GbE' of git://git.kernel.org/pub/scm/linux/kernel/git/tnguy/next-queue:
  e1000e: Fix real-time violations on link up
  igc: Avoid unnecessary link down event in XDP_SETUP_PROG process
  ice: refactor ice_fdir_create_dflt_rules() function
  ice: Implement PTP support for E830 devices
  ice: Refactor ice_ptp_init_tx_*
  ice: Add unified ice_capture_crosststamp
  ice: Process TSYN IRQ in a separate function
  ice: Use FIELD_PREP for timestamp values
  ice: Remove unnecessary ice_is_e8xx() functions
  ice: Don't check device type when checking GNSS presence
====================

Link: https://patch.msgid.link/20250210192352.3799673-1-anthony.l.nguyen@intel.com


Signed-off-by: default avatarJakub Kicinski <kuba@kernel.org>
parents be1d2a1b 13e22972
Loading
Loading
Loading
Loading
+1 −1
Original line number Diff line number Diff line
@@ -336,7 +336,7 @@ config ICE_SWITCHDEV
config ICE_HWTS
	bool "Support HW cross-timestamp on platforms with PTM support"
	default y
	depends on ICE && X86
	depends on ICE && X86 && PCIE_PTM
	help
	  Say Y to enable hardware supported cross-timestamping on platforms
	  with PCIe PTM support. The cross-timestamp is available through
+14 −1
Original line number Diff line number Diff line
@@ -331,8 +331,21 @@ void e1000e_update_mc_addr_list_generic(struct e1000_hw *hw,
	}

	/* replace the entire MTA table */
	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
	for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) {
		E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, hw->mac.mta_shadow[i]);

		if (IS_ENABLED(CONFIG_PREEMPT_RT)) {
			/*
			 * Do not queue up too many posted writes to prevent
			 * increased latency for other devices on the
			 * interconnect. Flush after each 8th posted write,
			 * to keep additional execution time low while still
			 * preventing increased latency.
			 */
			if (!(i % 8) && i)
				e1e_flush();
		}
	}
	e1e_flush();
}

+0 −5
Original line number Diff line number Diff line
@@ -1046,10 +1046,5 @@ static inline void ice_clear_rdma_cap(struct ice_pf *pf)
	clear_bit(ICE_FLAG_RDMA_ENA, pf->flags);
}

static inline enum ice_phy_model ice_get_phy_model(const struct ice_hw *hw)
{
	return hw->ptp.phy_model;
}

extern const struct xdp_metadata_ops ice_xdp_md_ops;
#endif /* _ICE_H_ */
+92 −116
Original line number Diff line number Diff line
@@ -186,7 +186,7 @@ static int ice_set_mac_type(struct ice_hw *hw)
 * ice_is_generic_mac - check if device's mac_type is generic
 * @hw: pointer to the hardware structure
 *
 * Return: true if mac_type is generic (with SBQ support), false if not
 * Return: true if mac_type is ICE_MAC_GENERIC*, false otherwise.
 */
bool ice_is_generic_mac(struct ice_hw *hw)
{
@@ -194,120 +194,6 @@ bool ice_is_generic_mac(struct ice_hw *hw)
		hw->mac_type == ICE_MAC_GENERIC_3K_E825);
}

/**
 * ice_is_e810
 * @hw: pointer to the hardware structure
 *
 * returns true if the device is E810 based, false if not.
 */
bool ice_is_e810(struct ice_hw *hw)
{
	return hw->mac_type == ICE_MAC_E810;
}

/**
 * ice_is_e810t
 * @hw: pointer to the hardware structure
 *
 * returns true if the device is E810T based, false if not.
 */
bool ice_is_e810t(struct ice_hw *hw)
{
	switch (hw->device_id) {
	case ICE_DEV_ID_E810C_SFP:
		switch (hw->subsystem_device_id) {
		case ICE_SUBDEV_ID_E810T:
		case ICE_SUBDEV_ID_E810T2:
		case ICE_SUBDEV_ID_E810T3:
		case ICE_SUBDEV_ID_E810T4:
		case ICE_SUBDEV_ID_E810T6:
		case ICE_SUBDEV_ID_E810T7:
			return true;
		}
		break;
	case ICE_DEV_ID_E810C_QSFP:
		switch (hw->subsystem_device_id) {
		case ICE_SUBDEV_ID_E810T2:
		case ICE_SUBDEV_ID_E810T3:
		case ICE_SUBDEV_ID_E810T5:
			return true;
		}
		break;
	default:
		break;
	}

	return false;
}

/**
 * ice_is_e822 - Check if a device is E822 family device
 * @hw: pointer to the hardware structure
 *
 * Return: true if the device is E822 based, false if not.
 */
bool ice_is_e822(struct ice_hw *hw)
{
	switch (hw->device_id) {
	case ICE_DEV_ID_E822C_BACKPLANE:
	case ICE_DEV_ID_E822C_QSFP:
	case ICE_DEV_ID_E822C_SFP:
	case ICE_DEV_ID_E822C_10G_BASE_T:
	case ICE_DEV_ID_E822C_SGMII:
	case ICE_DEV_ID_E822L_BACKPLANE:
	case ICE_DEV_ID_E822L_SFP:
	case ICE_DEV_ID_E822L_10G_BASE_T:
	case ICE_DEV_ID_E822L_SGMII:
		return true;
	default:
		return false;
	}
}

/**
 * ice_is_e823
 * @hw: pointer to the hardware structure
 *
 * returns true if the device is E823-L or E823-C based, false if not.
 */
bool ice_is_e823(struct ice_hw *hw)
{
	switch (hw->device_id) {
	case ICE_DEV_ID_E823L_BACKPLANE:
	case ICE_DEV_ID_E823L_SFP:
	case ICE_DEV_ID_E823L_10G_BASE_T:
	case ICE_DEV_ID_E823L_1GBE:
	case ICE_DEV_ID_E823L_QSFP:
	case ICE_DEV_ID_E823C_BACKPLANE:
	case ICE_DEV_ID_E823C_QSFP:
	case ICE_DEV_ID_E823C_SFP:
	case ICE_DEV_ID_E823C_10G_BASE_T:
	case ICE_DEV_ID_E823C_SGMII:
		return true;
	default:
		return false;
	}
}

/**
 * ice_is_e825c - Check if a device is E825C family device
 * @hw: pointer to the hardware structure
 *
 * Return: true if the device is E825-C based, false if not.
 */
bool ice_is_e825c(struct ice_hw *hw)
{
	switch (hw->device_id) {
	case ICE_DEV_ID_E825C_BACKPLANE:
	case ICE_DEV_ID_E825C_QSFP:
	case ICE_DEV_ID_E825C_SFP:
	case ICE_DEV_ID_E825C_SGMII:
		return true;
	default:
		return false;
	}
}

/**
 * ice_is_pf_c827 - check if pf contains c827 phy
 * @hw: pointer to the hw struct
@@ -2408,7 +2294,7 @@ ice_parse_1588_func_caps(struct ice_hw *hw, struct ice_hw_func_caps *func_p,
	info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0);
	info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0);

	if (!ice_is_e825c(hw)) {
	if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) {
		info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number);
		info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0);
	} else {
@@ -5764,6 +5650,96 @@ ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
	return ice_aq_send_cmd(hw, &desc, NULL, 0, cd);
}

/**
 * ice_get_pca9575_handle - find and return the PCA9575 controller
 * @hw: pointer to the hw struct
 * @pca9575_handle: GPIO controller's handle
 *
 * Find and return the GPIO controller's handle in the netlist.
 * When found - the value will be cached in the hw structure and following calls
 * will return cached value.
 *
 * Return: 0 on success, -ENXIO when there's no PCA9575 present.
 */
int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle)
{
	struct ice_aqc_get_link_topo *cmd;
	struct ice_aq_desc desc;
	int err;
	u8 idx;

	/* If handle was read previously return cached value */
	if (hw->io_expander_handle) {
		*pca9575_handle = hw->io_expander_handle;
		return 0;
	}

#define SW_PCA9575_SFP_TOPO_IDX		2
#define SW_PCA9575_QSFP_TOPO_IDX	1

	/* Check if the SW IO expander controlling SMA exists in the netlist. */
	if (hw->device_id == ICE_DEV_ID_E810C_SFP)
		idx = SW_PCA9575_SFP_TOPO_IDX;
	else if (hw->device_id == ICE_DEV_ID_E810C_QSFP)
		idx = SW_PCA9575_QSFP_TOPO_IDX;
	else
		return -ENXIO;

	/* If handle was not detected read it from the netlist */
	ice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);
	cmd = &desc.params.get_link_topo;
	cmd->addr.topo_params.node_type_ctx =
		ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL;
	cmd->addr.topo_params.index = idx;

	err = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);
	if (err)
		return -ENXIO;

	/* Verify if we found the right IO expander type */
	if (desc.params.get_link_topo.node_part_num !=
	    ICE_AQC_GET_LINK_TOPO_NODE_NR_PCA9575)
		return -ENXIO;

	/* If present save the handle and return it */
	hw->io_expander_handle =
		le16_to_cpu(desc.params.get_link_topo.addr.handle);
	*pca9575_handle = hw->io_expander_handle;

	return 0;
}

/**
 * ice_read_pca9575_reg - read the register from the PCA9575 controller
 * @hw: pointer to the hw struct
 * @offset: GPIO controller register offset
 * @data: pointer to data to be read from the GPIO controller
 *
 * Return: 0 on success, negative error code otherwise.
 */
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)
{
	struct ice_aqc_link_topo_addr link_topo;
	__le16 addr;
	u16 handle;
	int err;

	memset(&link_topo, 0, sizeof(link_topo));

	err = ice_get_pca9575_handle(hw, &handle);
	if (err)
		return err;

	link_topo.handle = cpu_to_le16(handle);
	link_topo.topo_params.node_type_ctx =
		FIELD_PREP(ICE_AQC_LINK_TOPO_NODE_CTX_M,
			   ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED);

	addr = cpu_to_le16((u16)offset);

	return ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);
}

/**
 * ice_aq_set_gpio
 * @hw: pointer to the hw struct
+2 −5
Original line number Diff line number Diff line
@@ -131,7 +131,6 @@ int
ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
			struct ice_sq_cd *cd);
bool ice_is_generic_mac(struct ice_hw *hw);
bool ice_is_e810(struct ice_hw *hw);
int ice_clear_pf_cfg(struct ice_hw *hw);
int
ice_aq_set_phy_cfg(struct ice_hw *hw, struct ice_port_info *pi,
@@ -276,10 +275,6 @@ ice_stat_update40(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
void
ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
		  u64 *prev_stat, u64 *cur_stat);
bool ice_is_e810t(struct ice_hw *hw);
bool ice_is_e822(struct ice_hw *hw);
bool ice_is_e823(struct ice_hw *hw);
bool ice_is_e825c(struct ice_hw *hw);
int
ice_sched_query_elem(struct ice_hw *hw, u32 node_teid,
		     struct ice_aqc_txsched_elem_data *buf);
@@ -306,5 +301,7 @@ int
ice_aq_write_i2c(struct ice_hw *hw, struct ice_aqc_link_topo_addr topo_addr,
		 u16 bus_addr, __le16 addr, u8 params, const u8 *data,
		 struct ice_sq_cd *cd);
int ice_get_pca9575_handle(struct ice_hw *hw, u16 *pca9575_handle);
int ice_read_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);
bool ice_fw_supports_report_dflt_cfg(struct ice_hw *hw);
#endif /* _ICE_COMMON_H_ */
Loading