Commit 4e4a4f58 authored by Chen Wang's avatar Chen Wang Committed by Manivannan Sadhasivam
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dt-bindings: pci: Add Sophgo SG2042 PCIe host

parent 8f5ae30d
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+64 −0
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# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)

description:
  Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.

maintainers:
  - Chen Wang <unicorn_wang@outlook.com>

properties:
  compatible:
    const: sophgo,sg2042-pcie-host

  reg:
    maxItems: 2

  reg-names:
    items:
      - const: reg
      - const: cfg

  vendor-id:
    const: 0x1f1c

  device-id:
    const: 0x2042

  msi-parent: true

allOf:
  - $ref: cdns-pcie-host.yaml#

required:
  - compatible
  - reg
  - reg-names

unevaluatedProperties: false

examples:
  - |
    #include <dt-bindings/interrupt-controller/irq.h>

    pcie@62000000 {
      compatible = "sophgo,sg2042-pcie-host";
      device_type = "pci";
      reg = <0x62000000  0x00800000>,
            <0x48000000  0x00001000>;
      reg-names = "reg", "cfg";
      #address-cells = <3>;
      #size-cells = <2>;
      ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
               <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
      bus-range = <0x00 0xff>;
      vendor-id = <0x1f1c>;
      device-id = <0x2042>;
      cdns,no-bar-match-nbits = <48>;
      msi-parent = <&msi>;
    };