Commit 4e591b89 authored by Thierry Bultel's avatar Thierry Bultel Committed by Geert Uytterhoeven
Browse files

dt-bindings: clock: renesas,cpg-mssr: Document RZ/T2H support 



Document RZ/T2H (a.k.a. r9a09g077) cpg-mssr (Clock Pulse Generator)
binding.

Reviewed-by: default avatar"Rob Herring (Arm)" <robh@kernel.org>
Signed-off-by: default avatarThierry Bultel <thierry.bultel.yh@bp.renesas.com>
Reviewed-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20250515141828.43444-3-thierry.bultel.yh@bp.renesas.com


Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
parent 6147c5f0

Documentation/devicetree/bindings/clock/renesas,cpg-mssr.yaml

+35 −11
Original line number Diff line number Diff line
@@ -52,9 +52,15 @@ properties: 
      - renesas,r8a779f0-cpg-mssr # R-Car S4-8

      - renesas,r8a779g0-cpg-mssr # R-Car V4H

      - renesas,r8a779h0-cpg-mssr # R-Car V4M

      - renesas,r9a09g077-cpg-mssr # RZ/T2H



  reg:

    maxItems: 1

    minItems: 1

    items:

      - description: base address of register block 0

      - description: base address of register block 1

    description: base addresses of clock controller. Some controllers

      (like r9a09g077) use two blocks instead of a single one.



  clocks:

    minItems: 1
@@ -92,7 +98,33 @@ properties: 
      the datasheet.

    const: 1



if:



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'



allOf:

  - if:

      properties:

        compatible:

          contains:

            const: renesas,r9a09g077-cpg-mssr

    then:

      properties:

        reg:

          minItems: 2

        clock-names:

          items:

            - const: extal

    else:

      properties:

        reg:

          maxItems: 1

  - if:

      not:

        properties:

          compatible:
@@ -103,14 +135,6 @@ then: 
      required:

        - '#reset-cells'



required:

  - compatible

  - reg

  - clocks

  - clock-names

  - '#clock-cells'

  - '#power-domain-cells'



additionalProperties: false



examples:

include/dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h

0 → 100644
+27 −0
Original line number Diff line number Diff line 
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)

 *

 * Copyright (C) 2025 Renesas Electronics Corp.

 */



#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__

#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__



#include <dt-bindings/clock/renesas-cpg-mssr.h>



/* R9A09G077 CPG Core Clocks */

#define R9A09G077_CLK_CA55C0		0

#define R9A09G077_CLK_CA55C1		1

#define R9A09G077_CLK_CA55C2		2

#define R9A09G077_CLK_CA55C3		3

#define R9A09G077_CLK_CA55S		4

#define R9A09G077_CLK_CR52_CPU0		5

#define R9A09G077_CLK_CR52_CPU1		6

#define R9A09G077_CLK_CKIO		7

#define R9A09G077_CLK_PCLKAH		8

#define R9A09G077_CLK_PCLKAM		9

#define R9A09G077_CLK_PCLKAL		10

#define R9A09G077_CLK_PCLKGPTL		11

#define R9A09G077_CLK_PCLKH		12

#define R9A09G077_CLK_PCLKM		13



#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G077_CPG_H__ */