Commit 4ee5d5ff authored by Oliver Upton's avatar Oliver Upton
Browse files

KVM: arm64: nv: Honor MDCR_EL2.{TPM, TPMCR} in Host EL0 



TPM and TPMCR trap bits also affect Host EL0. How fun.

Mark these two trap bits as such and take advantage of the new
infrastructure for dealing w/ EL0 traps.

Reviewed-by: default avatarMarc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20241025182354.3364124-10-oliver.upton@linux.dev


Signed-off-by: default avatarOliver Upton <oliver.upton@linux.dev>
parent d97e66fb

arch/arm64/kvm/emulate-nested.c

+4 −2
Original line number Diff line number Diff line
@@ -304,13 +304,15 @@ static const struct trap_bits coarse_trap_bits[] = { 
		.index		= MDCR_EL2,

		.value		= MDCR_EL2_TPMCR,

		.mask		= MDCR_EL2_TPMCR,

		.behaviour	= BEHAVE_FORWARD_RW,

		.behaviour	= BEHAVE_FORWARD_RW |

				  BEHAVE_FORWARD_IN_HOST_EL0,

	},

	[CGT_MDCR_TPM] = {

		.index		= MDCR_EL2,

		.value		= MDCR_EL2_TPM,

		.mask		= MDCR_EL2_TPM,

		.behaviour	= BEHAVE_FORWARD_RW,

		.behaviour	= BEHAVE_FORWARD_RW |

				  BEHAVE_FORWARD_IN_HOST_EL0,

	},

	[CGT_MDCR_TDE] = {

		.index		= MDCR_EL2,