Commit 4f37dc46 authored by Christophe Roullier's avatar Christophe Roullier Committed by Paolo Abeni
Browse files

net: stmmac: dwmac-stm32: Mask support for PMCR configuration 



Add possibility to have second argument in syscon property to manage
mask. This mask will be used to address right BITFIELDS of PMCR register.

Signed-off-by: default avatarChristophe Roullier <christophe.roullier@foss.st.com>
Reviewed-by: default avatarMarek Vasut <marex@denx.de>
Signed-off-by: default avatarPaolo Abeni <pabeni@redhat.com>
parent cbfad553

drivers/net/ethernet/stmicro/stmmac/dwmac-stm32.c

+19 −9
Original line number Diff line number Diff line
@@ -90,6 +90,7 @@ struct stm32_dwmac { 
	int eth_ref_clk_sel_reg;

	int irq_pwr_wakeup;

	u32 mode_reg;		 /* MAC glue-logic mode register */

	u32 mode_mask;

	struct regmap *regmap;

	u32 speed;

	const struct stm32_ops *ops;
@@ -102,8 +103,8 @@ struct stm32_ops { 
	void (*resume)(struct stm32_dwmac *dwmac);

	int (*parse_data)(struct stm32_dwmac *dwmac,

			  struct device *dev);

	u32 syscfg_eth_mask;

	bool clk_rx_enable_in_suspend;

	u32 syscfg_clr_off;

};



static int stm32_dwmac_clk_enable(struct stm32_dwmac *dwmac, bool resume)
@@ -256,13 +257,16 @@ static int stm32mp1_configure_pmcr(struct plat_stmmacenet_data *plat_dat) 


	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));



	/* Shift value at correct ethernet MAC offset in SYSCFG_PMCSETR */

	val <<= ffs(dwmac->mode_mask) - ffs(SYSCFG_MP1_ETH_MASK);



	/* Need to update PMCCLRR (clear register) */

	regmap_write(dwmac->regmap, reg + SYSCFG_PMCCLRR_OFFSET,

		     dwmac->ops->syscfg_eth_mask);

	regmap_write(dwmac->regmap, dwmac->ops->syscfg_clr_off,

		     dwmac->mode_mask);



	/* Update PMCSETR (set register) */

	return regmap_update_bits(dwmac->regmap, reg,

				 dwmac->ops->syscfg_eth_mask, val);

				 dwmac->mode_mask, val);

}



static int stm32mp1_set_mode(struct plat_stmmacenet_data *plat_dat)
@@ -303,7 +307,7 @@ static int stm32mcu_set_mode(struct plat_stmmacenet_data *plat_dat) 
	dev_dbg(dwmac->dev, "Mode %s", phy_modes(plat_dat->mac_interface));



	return regmap_update_bits(dwmac->regmap, reg,

				 dwmac->ops->syscfg_eth_mask, val << 23);

				 SYSCFG_MCU_ETH_MASK, val << 23);

}



static void stm32_dwmac_clk_disable(struct stm32_dwmac *dwmac, bool suspend)
@@ -348,8 +352,15 @@ static int stm32_dwmac_parse_data(struct stm32_dwmac *dwmac, 
		return PTR_ERR(dwmac->regmap);



	err = of_property_read_u32_index(np, "st,syscon", 1, &dwmac->mode_reg);

	if (err)

	if (err) {

		dev_err(dev, "Can't get sysconfig mode offset (%d)\n", err);

		return err;

	}



	dwmac->mode_mask = SYSCFG_MP1_ETH_MASK;

	err = of_property_read_u32_index(np, "st,syscon", 2, &dwmac->mode_mask);

	if (err)

		dev_dbg(dev, "Warning sysconfig register mask not set\n");



	return err;

}
@@ -540,8 +551,7 @@ static SIMPLE_DEV_PM_OPS(stm32_dwmac_pm_ops, 
	stm32_dwmac_suspend, stm32_dwmac_resume);



static struct stm32_ops stm32mcu_dwmac_data = {

	.set_mode = stm32mcu_set_mode,

	.syscfg_eth_mask = SYSCFG_MCU_ETH_MASK

	.set_mode = stm32mcu_set_mode

};



static struct stm32_ops stm32mp1_dwmac_data = {
@@ -549,7 +559,7 @@ static struct stm32_ops stm32mp1_dwmac_data = { 
	.suspend = stm32mp1_suspend,

	.resume = stm32mp1_resume,

	.parse_data = stm32mp1_parse_data,

	.syscfg_eth_mask = SYSCFG_MP1_ETH_MASK,

	.syscfg_clr_off = 0x44,

	.clk_rx_enable_in_suspend = true

};