Commit 4f412f79 authored by Victor Shih's avatar Victor Shih Committed by Ulf Hansson
Browse files

mmc: sdhci-uhs2: add related functions to initialize the interface 



UHS-II interface (related registers) will be initialized here. The
operations include mmc's uhs2_set_reg operations, mmc's uhs2_detect_init
operations, uhs2_[enable|disable]_clk operations. After detected the UHS-II
interface, the host's UHS-II capabilities will be set up here and
interrupts will also be enabled.

Signed-off-by: default avatarBen Chuang <ben.chuang@genesyslogic.com.tw>
Signed-off-by: default avatarAKASHI Takahiro <takahiro.akashi@linaro.org>
Signed-off-by: default avatarVictor Shih <victor.shih@genesyslogic.com.tw>
Acked-by: default avatarAdrian Hunter <adrian.hunter@intel.com>
Message-ID: <20241018105333.4569-11-victorshihgli@gmail.com>
Signed-off-by: default avatarUlf Hansson <ulf.hansson@linaro.org>
parent 10c8298a

drivers/mmc/host/sdhci-uhs2.c

+204 −0
Original line number Diff line number Diff line
@@ -26,6 +26,9 @@ 
	pr_err("%s: " DRIVER_NAME ": " f, mmc_hostname(host->mmc), ## x)



#define UHS2_RESET_TIMEOUT_100MS		100000

#define UHS2_CHECK_DORMANT_TIMEOUT_100MS	100000

#define UHS2_INTERFACE_DETECT_TIMEOUT_100MS	100000

#define UHS2_LANE_SYNC_TIMEOUT_150MS		150000



void sdhci_uhs2_dump_regs(struct sdhci_host *host)

{
@@ -303,6 +306,186 @@ static int sdhci_uhs2_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 
	return 0;

}



static int sdhci_uhs2_interface_detect(struct sdhci_host *host)

{

	u32 val;



	if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IF_DETECT),

			      100, UHS2_INTERFACE_DETECT_TIMEOUT_100MS, true,

			      host, SDHCI_PRESENT_STATE)) {

		pr_warn("%s: not detect UHS2 interface in 100ms.\n", mmc_hostname(host->mmc));

		sdhci_dumpregs(host);

		return -EIO;

	}



	/* Enable UHS2 error interrupts */

	sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK);



	if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_LANE_SYNC),

			      100, UHS2_LANE_SYNC_TIMEOUT_150MS, true, host, SDHCI_PRESENT_STATE)) {

		pr_warn("%s: UHS2 Lane sync fail in 150ms.\n", mmc_hostname(host->mmc));

		sdhci_dumpregs(host);

		return -EIO;

	}



	DBG("%s: UHS2 Lane synchronized in UHS2 mode, PHY is initialized.\n",

	    mmc_hostname(host->mmc));

	return 0;

}



static int sdhci_uhs2_init(struct sdhci_host *host)

{

	u16 caps_ptr = 0;

	u32 caps_gen = 0;

	u32 caps_phy = 0;

	u32 caps_tran[2] = {0, 0};

	struct mmc_host *mmc = host->mmc;



	caps_ptr = sdhci_readw(host, SDHCI_UHS2_CAPS_PTR);

	if (caps_ptr < 0x100 || caps_ptr > 0x1FF) {

		pr_err("%s: SDHCI_UHS2_CAPS_PTR(%d) is wrong.\n",

		       mmc_hostname(mmc), caps_ptr);

		return -ENODEV;

	}

	caps_gen = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_OFFSET);

	caps_phy = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_PHY_OFFSET);

	caps_tran[0] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_OFFSET);

	caps_tran[1] = sdhci_readl(host, caps_ptr + SDHCI_UHS2_CAPS_TRAN_1_OFFSET);



	/* General Caps */

	mmc->uhs2_caps.dap = caps_gen & SDHCI_UHS2_CAPS_DAP_MASK;

	mmc->uhs2_caps.gap = FIELD_GET(SDHCI_UHS2_CAPS_GAP_MASK, caps_gen);

	mmc->uhs2_caps.n_lanes = FIELD_GET(SDHCI_UHS2_CAPS_LANE_MASK, caps_gen);

	mmc->uhs2_caps.addr64 =	(caps_gen & SDHCI_UHS2_CAPS_ADDR_64) ? 1 : 0;

	mmc->uhs2_caps.card_type = FIELD_GET(SDHCI_UHS2_CAPS_DEV_TYPE_MASK, caps_gen);



	/* PHY Caps */

	mmc->uhs2_caps.phy_rev = caps_phy & SDHCI_UHS2_CAPS_PHY_REV_MASK;

	mmc->uhs2_caps.speed_range = FIELD_GET(SDHCI_UHS2_CAPS_PHY_RANGE_MASK, caps_phy);

	mmc->uhs2_caps.n_lss_sync = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_SYN_MASK, caps_phy);

	mmc->uhs2_caps.n_lss_dir = FIELD_GET(SDHCI_UHS2_CAPS_PHY_N_LSS_DIR_MASK, caps_phy);

	if (mmc->uhs2_caps.n_lss_sync == 0)

		mmc->uhs2_caps.n_lss_sync = 16 << 2;

	else

		mmc->uhs2_caps.n_lss_sync <<= 2;

	if (mmc->uhs2_caps.n_lss_dir == 0)

		mmc->uhs2_caps.n_lss_dir = 16 << 3;

	else

		mmc->uhs2_caps.n_lss_dir <<= 3;



	/* LINK/TRAN Caps */

	mmc->uhs2_caps.link_rev = caps_tran[0] & SDHCI_UHS2_CAPS_TRAN_LINK_REV_MASK;

	mmc->uhs2_caps.n_fcu = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_N_FCU_MASK, caps_tran[0]);

	if (mmc->uhs2_caps.n_fcu == 0)

		mmc->uhs2_caps.n_fcu = 256;

	mmc->uhs2_caps.host_type = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_HOST_TYPE_MASK, caps_tran[0]);

	mmc->uhs2_caps.maxblk_len = FIELD_GET(SDHCI_UHS2_CAPS_TRAN_BLK_LEN_MASK, caps_tran[0]);

	mmc->uhs2_caps.n_data_gap = caps_tran[1] & SDHCI_UHS2_CAPS_TRAN_1_N_DATA_GAP_MASK;



	return 0;

}



static int sdhci_uhs2_do_detect_init(struct mmc_host *mmc)

{

	struct sdhci_host *host = mmc_priv(mmc);



	DBG("Begin do uhs2 detect init.\n");



	if (sdhci_uhs2_interface_detect(host)) {

		pr_warn("%s: cannot detect UHS2 interface.\n", mmc_hostname(host->mmc));

		return -EIO;

	}



	if (sdhci_uhs2_init(host)) {

		pr_warn("%s: UHS2 init fail.\n", mmc_hostname(host->mmc));

		return -EIO;

	}



	/* Init complete, do soft reset and enable UHS2 error irqs. */

	sdhci_uhs2_reset(host, SDHCI_UHS2_SW_RESET_SD);

	sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_ALL_MASK, SDHCI_UHS2_INT_ERROR_MASK);

	/*

	 * N.B SDHCI_INT_ENABLE and SDHCI_SIGNAL_ENABLE was cleared

	 * by SDHCI_UHS2_SW_RESET_SD

	 */

	sdhci_writel(host, host->ier, SDHCI_INT_ENABLE);

	sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE);



	return 0;

}



static int sdhci_uhs2_disable_clk(struct mmc_host *mmc)

{

	struct sdhci_host *host = mmc_priv(mmc);

	u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);



	clk &= ~SDHCI_CLOCK_CARD_EN;

	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);



	return 0;

}



static int sdhci_uhs2_enable_clk(struct mmc_host *mmc)

{

	struct sdhci_host *host = mmc_priv(mmc);

	u16 clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);

	int timeout_us = 20000; /* 20ms */

	u32 val;



	clk |= SDHCI_CLOCK_CARD_EN;

	sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);



	if (read_poll_timeout(sdhci_readw, val, (val & SDHCI_CLOCK_INT_STABLE),

			      10, timeout_us, true, host, SDHCI_CLOCK_CONTROL)) {

		pr_err("%s: Internal clock never stabilised.\n", mmc_hostname(host->mmc));

		sdhci_dumpregs(host);

		return -EIO;

	}

	return 0;

}



static void sdhci_uhs2_set_config(struct sdhci_host *host)

{

	u32 value;

	u16 sdhci_uhs2_set_ptr = sdhci_readw(host, SDHCI_UHS2_SETTINGS_PTR);

	u16 sdhci_uhs2_gen_set_reg	= sdhci_uhs2_set_ptr;

	u16 sdhci_uhs2_phy_set_reg	= sdhci_uhs2_set_ptr + 4;

	u16 sdhci_uhs2_tran_set_reg	= sdhci_uhs2_set_ptr + 8;

	u16 sdhci_uhs2_tran_set_1_reg	= sdhci_uhs2_set_ptr + 12;



	/* Set Gen Settings */

	value = FIELD_PREP(SDHCI_UHS2_GEN_SETTINGS_N_LANES_MASK, host->mmc->uhs2_caps.n_lanes_set);

	sdhci_writel(host, value, sdhci_uhs2_gen_set_reg);



	/* Set PHY Settings */

	value = FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_DIR_MASK, host->mmc->uhs2_caps.n_lss_dir_set) |

		FIELD_PREP(SDHCI_UHS2_PHY_N_LSS_SYN_MASK, host->mmc->uhs2_caps.n_lss_sync_set);

	if (host->mmc->ios.timing == MMC_TIMING_UHS2_SPEED_B ||

	    host->mmc->ios.timing == MMC_TIMING_UHS2_SPEED_B_HD)

		value |= SDHCI_UHS2_PHY_SET_SPEED_B;

	sdhci_writel(host, value, sdhci_uhs2_phy_set_reg);



	/* Set LINK-TRAN Settings */

	value = FIELD_PREP(SDHCI_UHS2_TRAN_RETRY_CNT_MASK, host->mmc->uhs2_caps.max_retry_set) |

		FIELD_PREP(SDHCI_UHS2_TRAN_N_FCU_MASK, host->mmc->uhs2_caps.n_fcu_set);

	sdhci_writel(host, value, sdhci_uhs2_tran_set_reg);

	sdhci_writel(host, host->mmc->uhs2_caps.n_data_gap_set, sdhci_uhs2_tran_set_1_reg);

}



static int sdhci_uhs2_check_dormant(struct sdhci_host *host)

{

	u32 val;



	if (read_poll_timeout(sdhci_readl, val, (val & SDHCI_UHS2_IN_DORMANT_STATE),

			      100, UHS2_CHECK_DORMANT_TIMEOUT_100MS, true, host,

			      SDHCI_PRESENT_STATE)) {

		pr_warn("%s: UHS2 IN_DORMANT fail in 100ms.\n", mmc_hostname(host->mmc));

		sdhci_dumpregs(host);

		return -EIO;

	}

	return 0;

}



static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation op)

{

	struct sdhci_host *host = mmc_priv(mmc);
@@ -312,6 +495,27 @@ static int sdhci_uhs2_control(struct mmc_host *mmc, enum sd_uhs2_operation op) 
	DBG("Begin uhs2 control, act %d.\n", op);



	switch (op) {

	case UHS2_PHY_INIT:

		err = sdhci_uhs2_do_detect_init(mmc);

		break;

	case UHS2_SET_CONFIG:

		sdhci_uhs2_set_config(host);

		break;

	case UHS2_ENABLE_INT:

		sdhci_uhs2_clear_set_irqs(host, 0, SDHCI_INT_CARD_INT);

		break;

	case UHS2_DISABLE_INT:

		sdhci_uhs2_clear_set_irqs(host, SDHCI_INT_CARD_INT, 0);

		break;

	case UHS2_CHECK_DORMANT:

		err = sdhci_uhs2_check_dormant(host);

		break;

	case UHS2_DISABLE_CLK:

		err = sdhci_uhs2_disable_clk(mmc);

		break;

	case UHS2_ENABLE_CLK:

		err = sdhci_uhs2_enable_clk(mmc);

		break;

	case UHS2_SET_IOS:

		err = sdhci_uhs2_set_ios(mmc, ios);

		break;