Commit 4f543d66 authored by Ville Syrjälä's avatar Ville Syrjälä
Browse files

drm/i915: Require an exact DP link freq match for the DG2 PLL 



No idea why the DG2 PLL DP link frequency calculation is allowing
a non-exact match. That makes no sense so get rid of it.

Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220503182242.18797-24-ville.syrjala@linux.intel.com


Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Acked-by: default avatarMatt Roper <matthew.d.roper@intel.com>
parent f2206df8

drivers/gpu/drm/i915/display/intel_snps_phy.c

+1 −1
Original line number Diff line number Diff line
@@ -629,7 +629,7 @@ int intel_mpllb_calc_state(struct intel_crtc_state *crtc_state, 
		return -EINVAL;



	for (i = 0; tables[i]; i++) {

		if (crtc_state->port_clock <= tables[i]->clock) {

		if (crtc_state->port_clock == tables[i]->clock) {

			crtc_state->mpllb_state = *tables[i];

			return 0;

		}