Commit 4f9ffd2c authored by Icenowy Zheng's avatar Icenowy Zheng Committed by Christian König
Browse files

drm/ttm: add pgprot handling for RISC-V 



The RISC-V Svpbmt privileged extension provides support for overriding
page memory coherency attributes, and, along with vendor extensions like
Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.

Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
access attributes.

Signed-off-by: default avatarIcenowy Zheng <uwu@icenowy.me>
Tested-by: default avatarHan Gao <rabenda.cn@gmail.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarChristian König <christian.koenig@amd.com>
Link: https://lore.kernel.org/r/20251020053523.731353-1-uwu@icenowy.me
parent a80c98b6

drivers/gpu/drm/ttm/ttm_module.c

+2 −1
Original line number Diff line number Diff line
@@ -74,7 +74,8 @@ pgprot_t ttm_prot_from_caching(enum ttm_caching caching, pgprot_t tmp) 
#endif /* CONFIG_UML */

#endif /* __i386__ || __x86_64__ */

#if defined(__ia64__) || defined(__arm__) || defined(__aarch64__) || \

	defined(__powerpc__) || defined(__mips__) || defined(__loongarch__)

	defined(__powerpc__) || defined(__mips__) || defined(__loongarch__) || \

	defined(__riscv)

	if (caching == ttm_write_combined)

		tmp = pgprot_writecombine(tmp);

	else