Commit 4fde8953 authored by Dave Jiang's avatar Dave Jiang
Browse files

cxl: Add helper to detect top of CXL device topology 



Add a helper to replace the open code detection of CXL device hierarchy
root, or the host bridge. The helper will be used for delayed downstream
port (dport) creation.

Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: default avatarLi Ming <ming.li@zohomail.com>
Reviewed-by: default avatarDan Williams <dan.j.williams@intel.com>
Reviewed-by: default avatarAlison Schofield <alison.schofield@intel.com>
Reviewed-by: default avatarRobert Richter <rrichter@amd.com>
Tested-by: default avatarRobert Richter <rrichter@amd.com>
Signed-off-by: default avatarDave Jiang <dave.jiang@intel.com>
parent 8f5ae30d

drivers/cxl/core/port.c

+11 −6
Original line number Diff line number Diff line
@@ -33,6 +33,15 @@ 
static DEFINE_IDA(cxl_port_ida);

static DEFINE_XARRAY(cxl_root_buses);



/*

 * The terminal device in PCI is NULL and @platform_bus

 * for platform devices (for cxl_test)

 */

static bool is_cxl_host_bridge(struct device *dev)

{

	return (!dev || dev == &platform_bus);

}



int cxl_num_decoders_committed(struct cxl_port *port)

{

	lockdep_assert_held(&cxl_rwsem.region);
@@ -1541,7 +1550,7 @@ static int add_port_attach_ep(struct cxl_memdev *cxlmd, 
	resource_size_t component_reg_phys;

	int rc;



	if (!dparent) {

	if (is_cxl_host_bridge(dparent)) {

		/*

		 * The iteration reached the topology root without finding the

		 * CXL-root 'cxl_port' on a previous iteration, fail for now to
@@ -1629,11 +1638,7 @@ int devm_cxl_enumerate_ports(struct cxl_memdev *cxlmd) 
		struct device *uport_dev;

		struct cxl_dport *dport;



		/*

		 * The terminal "grandparent" in PCI is NULL and @platform_bus

		 * for platform devices

		 */

		if (!dport_dev || dport_dev == &platform_bus)

		if (is_cxl_host_bridge(dport_dev))

			return 0;



		uport_dev = dport_dev->parent;