Commit 50137c15 authored by Sam Shih's avatar Sam Shih Committed by Matthias Brugger
Browse files

arm64: dts: mediatek: add basic mt7986 support 



Add basic chip support for Mediatek mt7986, include
basic uart nodes, rng node and watchdog node.

Add cpu node, timer node, gic node, psci and reserved-memory node
for ARM Trusted Firmware.

Signed-off-by: default avatarSam Shih <sam.shih@mediatek.com>
Link: https://lore.kernel.org/r/20211122123222.8016-3-sam.shih@mediatek.com


Signed-off-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
parent 19ebf10e

arch/arm64/boot/dts/mediatek/Makefile

+1 −0
Original line number Diff line number Diff line
@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb 
dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-rfb.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8167-pumpkin.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm.dtb

dtb-$(CONFIG_ARCH_MEDIATEK) += mt8173-elm-hana.dtb

arch/arm64/boot/dts/mediatek/mt7986a-rfb.dts

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+37 −0
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*

 * Copyright (C) 2021 MediaTek Inc.

 * Author: Sam.Shih <sam.shih@mediatek.com>

 */



/dts-v1/;

#include "mt7986a.dtsi"



/ {

	model = "MediaTek MT7986a RFB";

	compatible = "mediatek,mt7986a-rfb";



	aliases {

		serial0 = &uart0;

	};



	chosen {

		stdout-path = "serial0:115200n8";

	};



	memory {

		reg = <0 0x40000000 0 0x40000000>;

	};

};



&uart0 {

	status = "okay";

};



&uart1 {

	status = "okay";

};



&uart2 {

	status = "okay";

};

arch/arm64/boot/dts/mediatek/mt7986a.dtsi

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+148 −0
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)

/*

 * Copyright (C) 2021 MediaTek Inc.

 * Author: Sam.Shih <sam.shih@mediatek.com>

 */



#include <dt-bindings/interrupt-controller/irq.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>



/ {

	interrupt-parent = <&gic>;

	#address-cells = <2>;

	#size-cells = <2>;



	system_clk: dummy40m {

		compatible = "fixed-clock";

		clock-frequency = <40000000>;

		#clock-cells = <0>;

	};



	cpus {

		#address-cells = <1>;

		#size-cells = <0>;

		cpu0: cpu@0 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x0>;

			#cooling-cells = <2>;

		};



		cpu1: cpu@1 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x1>;

			#cooling-cells = <2>;

		};



		cpu2: cpu@2 {

			device_type = "cpu";

			compatible = "arm,cortex-a53";

			enable-method = "psci";

			reg = <0x2>;

			#cooling-cells = <2>;

		};



		cpu3: cpu@3 {

			device_type = "cpu";

			enable-method = "psci";

			compatible = "arm,cortex-a53";

			reg = <0x3>;

			#cooling-cells = <2>;

		};

	};



	psci {

		compatible  = "arm,psci-0.2";

		method      = "smc";

	};



	reserved-memory {

		#address-cells = <2>;

		#size-cells = <2>;

		ranges;

		/* 192 KiB reserved for ARM Trusted Firmware (BL31) */

		secmon_reserved: secmon@43000000 {

			reg = <0 0x43000000 0 0x30000>;

			no-map;

		};

	};



	timer {

		compatible = "arm,armv8-timer";

		interrupt-parent = <&gic>;

		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,

			     <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;

	};



	soc {

		#address-cells = <2>;

		#size-cells = <2>;

		compatible = "simple-bus";

		ranges;



		gic: interrupt-controller@c000000 {

			compatible = "arm,gic-v3";

			#interrupt-cells = <3>;

			interrupt-parent = <&gic>;

			interrupt-controller;

			reg = <0 0x0c000000 0 0x10000>,  /* GICD */

			      <0 0x0c080000 0 0x80000>,  /* GICR */

			      <0 0x0c400000 0 0x2000>,   /* GICC */

			      <0 0x0c410000 0 0x1000>,   /* GICH */

			      <0 0x0c420000 0 0x2000>;   /* GICV */

			interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		};



		watchdog: watchdog@1001c000 {

			compatible = "mediatek,mt7986-wdt",

				     "mediatek,mt6589-wdt";

			reg = <0 0x1001c000 0 0x1000>;

			interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;

			#reset-cells = <1>;

			status = "disabled";

		};



		trng: trng@1020f000 {

			compatible = "mediatek,mt7986-rng",

				     "mediatek,mt7623-rng";

			reg = <0 0x1020f000 0 0x100>;

			clocks = <&system_clk>;

			clock-names = "rng";

			status = "disabled";

		};



		uart0: serial@11002000 {

			compatible = "mediatek,mt7986-uart",

				     "mediatek,mt6577-uart";

			reg = <0 0x11002000 0 0x400>;

			interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			status = "disabled";

		};



		uart1: serial@11003000 {

			compatible = "mediatek,mt7986-uart",

				     "mediatek,mt6577-uart";

			reg = <0 0x11003000 0 0x400>;

			interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			status = "disabled";

		};



		uart2: serial@11004000 {

			compatible = "mediatek,mt7986-uart",

				     "mediatek,mt6577-uart";

			reg = <0 0x11004000 0 0x400>;

			interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;

			clocks = <&system_clk>;

			status = "disabled";

		};



	};



};