Commit 502099e9 authored by Luca Weiss's avatar Luca Weiss Committed by Bjorn Andersson
Browse files

clk: qcom: dispcc-sm6350: Add MDSS_CORE & MDSS_RSCC resets 



Add the offsets for two resets inside the dispcc on SM6350 SoC.

Signed-off-by: default avatarLuca Weiss <luca.weiss@fairphone.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20250919-sm6350-mdss-reset-v1-2-48dcac917c73@fairphone.com


Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
parent ff71d2d8

drivers/clk/qcom/dispcc-sm6350.c

+7 −0
Original line number Diff line number Diff line
@@ -679,6 +679,11 @@ static struct clk_branch disp_cc_xo_clk = { 
	},

};



static const struct qcom_reset_map disp_cc_sm6350_resets[] = {

	[DISP_CC_MDSS_CORE_BCR] = { 0x1000 },

	[DISP_CC_MDSS_RSCC_BCR] = { 0x2000 },

};



static struct gdsc mdss_gdsc = {

	.gdscr = 0x1004,

	.en_rest_wait_val = 0x2,
@@ -746,6 +751,8 @@ static const struct qcom_cc_desc disp_cc_sm6350_desc = { 
	.num_clks = ARRAY_SIZE(disp_cc_sm6350_clocks),

	.gdscs = disp_cc_sm6350_gdscs,

	.num_gdscs = ARRAY_SIZE(disp_cc_sm6350_gdscs),

	.resets = disp_cc_sm6350_resets,

	.num_resets = ARRAY_SIZE(disp_cc_sm6350_resets),

};



static const struct of_device_id disp_cc_sm6350_match_table[] = {