Commit 50729632 authored by Alex Deucher's avatar Alex Deucher
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drm/amdgpu: Add additional DCE6 SCL registers 



Fixes: 102b2f58 ("drm/amd/display: dce_transform: DCE6 Scaling Horizontal Filter Init (v2)")
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent b2ec5ca9

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_d.h

+7 −0
Original line number Diff line number Diff line
@@ -4115,6 +4115,7 @@ 
#define mmSCL0_SCL_COEF_RAM_CONFLICT_STATUS 0x1B55

#define mmSCL0_SCL_COEF_RAM_SELECT 0x1B40

#define mmSCL0_SCL_COEF_RAM_TAP_DATA 0x1B41

#define mmSCL0_SCL_SCALER_ENABLE 0x1B42

#define mmSCL0_SCL_CONTROL 0x1B44

#define mmSCL0_SCL_DEBUG 0x1B6A

#define mmSCL0_SCL_DEBUG2 0x1B69
@@ -4144,6 +4145,7 @@ 
#define mmSCL1_SCL_COEF_RAM_CONFLICT_STATUS 0x1E55

#define mmSCL1_SCL_COEF_RAM_SELECT 0x1E40

#define mmSCL1_SCL_COEF_RAM_TAP_DATA 0x1E41

#define mmSCL1_SCL_SCALER_ENABLE 0x1E42

#define mmSCL1_SCL_CONTROL 0x1E44

#define mmSCL1_SCL_DEBUG 0x1E6A

#define mmSCL1_SCL_DEBUG2 0x1E69
@@ -4173,6 +4175,7 @@ 
#define mmSCL2_SCL_COEF_RAM_CONFLICT_STATUS 0x4155

#define mmSCL2_SCL_COEF_RAM_SELECT 0x4140

#define mmSCL2_SCL_COEF_RAM_TAP_DATA 0x4141

#define mmSCL2_SCL_SCALER_ENABLE 0x4142

#define mmSCL2_SCL_CONTROL 0x4144

#define mmSCL2_SCL_DEBUG 0x416A

#define mmSCL2_SCL_DEBUG2 0x4169
@@ -4202,6 +4205,7 @@ 
#define mmSCL3_SCL_COEF_RAM_CONFLICT_STATUS 0x4455

#define mmSCL3_SCL_COEF_RAM_SELECT 0x4440

#define mmSCL3_SCL_COEF_RAM_TAP_DATA 0x4441

#define mmSCL3_SCL_SCALER_ENABLE 0x4442

#define mmSCL3_SCL_CONTROL 0x4444

#define mmSCL3_SCL_DEBUG 0x446A

#define mmSCL3_SCL_DEBUG2 0x4469
@@ -4231,6 +4235,7 @@ 
#define mmSCL4_SCL_COEF_RAM_CONFLICT_STATUS 0x4755

#define mmSCL4_SCL_COEF_RAM_SELECT 0x4740

#define mmSCL4_SCL_COEF_RAM_TAP_DATA 0x4741

#define mmSCL4_SCL_SCALER_ENABLE 0x4742

#define mmSCL4_SCL_CONTROL 0x4744

#define mmSCL4_SCL_DEBUG 0x476A

#define mmSCL4_SCL_DEBUG2 0x4769
@@ -4260,6 +4265,7 @@ 
#define mmSCL5_SCL_COEF_RAM_CONFLICT_STATUS 0x4A55

#define mmSCL5_SCL_COEF_RAM_SELECT 0x4A40

#define mmSCL5_SCL_COEF_RAM_TAP_DATA 0x4A41

#define mmSCL5_SCL_SCALER_ENABLE 0x4A42

#define mmSCL5_SCL_CONTROL 0x4A44

#define mmSCL5_SCL_DEBUG 0x4A6A

#define mmSCL5_SCL_DEBUG2 0x4A69
@@ -4287,6 +4293,7 @@ 
#define mmSCL_COEF_RAM_CONFLICT_STATUS 0x1B55

#define mmSCL_COEF_RAM_SELECT 0x1B40

#define mmSCL_COEF_RAM_TAP_DATA 0x1B41

#define mmSCL_SCALER_ENABLE 0x1B42

#define mmSCL_CONTROL 0x1B44

#define mmSCL_DEBUG 0x1B6A

#define mmSCL_DEBUG2 0x1B69

drivers/gpu/drm/amd/include/asic_reg/dce/dce_6_0_sh_mask.h

+2 −0
Original line number Diff line number Diff line
@@ -8650,6 +8650,8 @@ 
#define REGAMMA_LUT_INDEX__REGAMMA_LUT_INDEX__SHIFT 0x00000000

#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK_MASK 0x00000007L

#define REGAMMA_LUT_WRITE_EN_MASK__REGAMMA_LUT_WRITE_EN_MASK__SHIFT 0x00000000

#define SCL_SCALER_ENABLE__SCL_SCALE_EN_MASK 0x00000001L

#define SCL_SCALER_ENABLE__SCL_SCALE_EN__SHIFT 0x00000000

#define SCL_ALU_CONTROL__SCL_ALU_DISABLE_MASK 0x00000001L

#define SCL_ALU_CONTROL__SCL_ALU_DISABLE__SHIFT 0x00000000

#define SCL_BYPASS_CONTROL__SCL_BYPASS_MODE_MASK 0x00000003L