Commit 5077b136 authored by Dmitry Baryshkov's avatar Dmitry Baryshkov Committed by Vinod Koul
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phy: qcom-qmp-usb: move PCS v6 register to the proper header 



The commit 39bbf82d ("phy: qcom-qmp: pcs-usb: Add v6 register
offsets") incorrectly added plain PCS registers to the PCS_USB header.
Move them to a proper location.

Signed-off-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20230928105445.1210861-3-dmitry.baryshkov@linaro.org


Signed-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 579483ec

drivers/phy/qualcomm/phy-qcom-qmp-pcs-usb-v6.h

+0 −16
Original line number Diff line number Diff line
@@ -7,22 +7,6 @@ 
#define QCOM_PHY_QMP_PCS_USB_V6_H_



/* Only for QMP V6 PHY - USB3 have different offsets than V5 */

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1		0xc4

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2		0xc8

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3		0xcc

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6		0xd8

#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1		0xdc

#define QPHY_V6_PCS_POWER_STATE_CONFIG1		0x90

#define QPHY_V6_PCS_RX_SIGDET_LVL			0x188

#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L		0x190

#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H		0x194

#define QPHY_V6_PCS_CDR_RESET_TIME			0x1b0

#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG1		0x1c0

#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG2		0x1c4

#define QPHY_V6_PCS_PCS_TX_RX_CONFIG		0x1d0

#define QPHY_V6_PCS_EQ_CONFIG1			0x1dc

#define QPHY_V6_PCS_EQ_CONFIG5			0x1ec



#define QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1		0x00

#define QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL	0x18

#define QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2	0x3c

drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h

+14 −2
Original line number Diff line number Diff line
@@ -7,10 +7,22 @@ 
#define QCOM_PHY_QMP_PCS_V6_H_



/* Only for QMP V6 PHY - USB/PCIe PCS registers */

#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1		0xdc

#define QPHY_V6_PCS_POWER_STATE_CONFIG1		0x090

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG1		0x0c4

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG2		0x0c8

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG3		0x0cc

#define QPHY_V6_PCS_LOCK_DETECT_CONFIG6		0x0d8

#define QPHY_V6_PCS_REFGEN_REQ_CONFIG1		0x0dc

#define QPHY_V6_PCS_RX_SIGDET_LVL		0x188

#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L	0x190

#define QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H	0x194

#define QPHY_V6_PCS_RATE_SLEW_CNTRL1		0x198

#define QPHY_V6_PCS_EQ_CONFIG2			0x1e0

#define QPHY_V6_PCS_CDR_RESET_TIME		0x1b0

#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG1	0x1c0

#define QPHY_V6_PCS_ALIGN_DETECT_CONFIG2	0x1c4

#define QPHY_V6_PCS_PCS_TX_RX_CONFIG		0x1d0

#define QPHY_V6_PCS_EQ_CONFIG1			0x1dc

#define QPHY_V6_PCS_EQ_CONFIG2			0x1e0

#define QPHY_V6_PCS_EQ_CONFIG5			0x1ec



#endif