Commit 50a9b75d authored by Odelu Kukatla's avatar Odelu Kukatla Committed by Georgi Djakov
Browse files

interconnect: qcom: qcs615: enable QoS configuration 



Enable QoS configuration for master ports with predefined priority
and urgency forwarding.

Signed-off-by: default avatarOdelu Kukatla <odelu.kukatla@oss.qualcomm.com>
Reviewed-by: default avatarKonrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://msgid.link/20260311103548.1823044-3-odelu.kukatla@oss.qualcomm.com


Signed-off-by: default avatarGeorgi Djakov <djakov@kernel.org>
parent e07f3b8c

drivers/interconnect/qcom/qcs615.c

+247 −0
Original line number Diff line number Diff line
@@ -142,6 +142,12 @@ static struct qcom_icc_node qhm_qdss_bam = { 
	.name = "qhm_qdss_bam",

	.channels = 1,

	.buswidth = 4,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xc000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -150,6 +156,12 @@ static struct qcom_icc_node qhm_qspi = { 
	.name = "qhm_qspi",

	.channels = 1,

	.buswidth = 4,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x17000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -158,6 +170,12 @@ static struct qcom_icc_node qhm_qup0 = { 
	.name = "qhm_qup0",

	.channels = 1,

	.buswidth = 4,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x10000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -166,6 +184,12 @@ static struct qcom_icc_node qhm_qup1 = { 
	.name = "qhm_qup1",

	.channels = 1,

	.buswidth = 4,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x12000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -174,6 +198,12 @@ static struct qcom_icc_node qnm_cnoc = { 
	.name = "qnm_cnoc",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x4000 },

		.prio = 2,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -182,6 +212,12 @@ static struct qcom_icc_node qxm_crypto = { 
	.name = "qxm_crypto",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x5000 },

		.prio = 2,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -190,6 +226,12 @@ static struct qcom_icc_node qxm_ipa = { 
	.name = "qxm_ipa",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x6000 },

		.prio = 2,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_lpass_snoc },

};
@@ -198,6 +240,12 @@ static struct qcom_icc_node xm_emac_avb = { 
	.name = "xm_emac_avb",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xa000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -206,6 +254,12 @@ static struct qcom_icc_node xm_pcie = { 
	.name = "xm_pcie",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x13000 },

		.prio = 0,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_pcie_snoc },

};
@@ -214,6 +268,12 @@ static struct qcom_icc_node xm_qdss_etr = { 
	.name = "xm_qdss_etr",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xb000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -222,6 +282,12 @@ static struct qcom_icc_node xm_sdc1 = { 
	.name = "xm_sdc1",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xe000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -230,6 +296,12 @@ static struct qcom_icc_node xm_sdc2 = { 
	.name = "xm_sdc2",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x16000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -238,6 +310,12 @@ static struct qcom_icc_node xm_ufs_mem = { 
	.name = "xm_ufs_mem",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x11000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -246,6 +324,12 @@ static struct qcom_icc_node xm_usb2 = { 
	.name = "xm_usb2",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x15000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -254,6 +338,12 @@ static struct qcom_icc_node xm_usb3_0 = { 
	.name = "xm_usb3_0",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xd000 },

		.prio = 2,

		.urg_fwd = 0,

	},

	.num_links = 1,

	.link_nodes = { &qns_a1noc_snoc },

};
@@ -356,6 +446,12 @@ static struct qcom_icc_node acm_apps = { 
	.name = "acm_apps",

	.channels = 1,

	.buswidth = 16,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 2,

		.port_offsets = { 0x2e000, 0x2e100 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 3,

	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc,

			&qns_sys_pcie },
@@ -365,6 +461,12 @@ static struct qcom_icc_node acm_gpu_tcu = { 
	.name = "acm_gpu_tcu",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x36000 },

		.prio = 6,

		.urg_fwd = 0,

	},

	.num_links = 2,

	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },

};
@@ -373,6 +475,12 @@ static struct qcom_icc_node acm_sys_tcu = { 
	.name = "acm_sys_tcu",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x37000 },

		.prio = 6,

		.urg_fwd = 0,

	},

	.num_links = 2,

	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },

};
@@ -389,6 +497,12 @@ static struct qcom_icc_node qnm_gpu = { 
	.name = "qnm_gpu",

	.channels = 2,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 2,

		.port_offsets = { 0x34000, 0x34080 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 2,

	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },

};
@@ -397,6 +511,12 @@ static struct qcom_icc_node qnm_mnoc_hf = { 
	.name = "qnm_mnoc_hf",

	.channels = 1,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x2f000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_llcc },

};
@@ -405,6 +525,12 @@ static struct qcom_icc_node qnm_mnoc_sf = { 
	.name = "qnm_mnoc_sf",

	.channels = 1,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x35000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 2,

	.link_nodes = { &qns_gem_noc_snoc, &qns_llcc },

};
@@ -413,6 +539,12 @@ static struct qcom_icc_node qnm_snoc_gc = { 
	.name = "qnm_snoc_gc",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x31000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_llcc },

};
@@ -421,6 +553,12 @@ static struct qcom_icc_node qnm_snoc_sf = { 
	.name = "qnm_snoc_sf",

	.channels = 1,

	.buswidth = 16,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x30000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_llcc },

};
@@ -445,6 +583,12 @@ static struct qcom_icc_node qxm_camnoc_hf0 = { 
	.name = "qxm_camnoc_hf0",

	.channels = 1,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xa000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_mem_noc_hf },

};
@@ -453,6 +597,12 @@ static struct qcom_icc_node qxm_camnoc_hf1 = { 
	.name = "qxm_camnoc_hf1",

	.channels = 1,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xb000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_mem_noc_hf },

};
@@ -461,6 +611,12 @@ static struct qcom_icc_node qxm_camnoc_sf = { 
	.name = "qxm_camnoc_sf",

	.channels = 1,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x9000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns2_mem_noc },

};
@@ -469,6 +625,12 @@ static struct qcom_icc_node qxm_mdp0 = { 
	.name = "qxm_mdp0",

	.channels = 1,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xc000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns_mem_noc_hf },

};
@@ -477,6 +639,12 @@ static struct qcom_icc_node qxm_rot = { 
	.name = "qxm_rot",

	.channels = 1,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xe000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns2_mem_noc },

};
@@ -485,6 +653,12 @@ static struct qcom_icc_node qxm_venus0 = { 
	.name = "qxm_venus0",

	.channels = 1,

	.buswidth = 32,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xf000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns2_mem_noc },

};
@@ -493,6 +667,12 @@ static struct qcom_icc_node qxm_venus_arm9 = { 
	.name = "qxm_venus_arm9",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0x11000 },

		.prio = 0,

		.urg_fwd = 1,

	},

	.num_links = 1,

	.link_nodes = { &qns2_mem_noc },

};
@@ -559,6 +739,12 @@ static struct qcom_icc_node qxm_pimem = { 
	.name = "qxm_pimem",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xc000 },

		.prio = 2,

		.urg_fwd = 1,

	},

	.num_links = 2,

	.link_nodes = { &qns_memnoc_gc, &qxs_imem },

};
@@ -567,6 +753,12 @@ static struct qcom_icc_node xm_gic = { 
	.name = "xm_gic",

	.channels = 1,

	.buswidth = 8,

	.qosbox = &(const struct qcom_icc_qosbox) {

		.num_ports = 1,

		.port_offsets = { 0xd000 },

		.prio = 2,

		.urg_fwd = 1,

	},

	.num_links = 2,

	.link_nodes = { &qns_memnoc_gc, &qxs_imem },

};
@@ -1213,11 +1405,21 @@ static struct qcom_icc_node * const aggre1_noc_nodes[] = { 
	[SLAVE_SERVICE_A2NOC] = &srvc_aggre2_noc,

};



static const struct regmap_config qcs615_aggre1_noc_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0x3f200,

	.fast_io = true,

};



static const struct qcom_icc_desc qcs615_aggre1_noc = {

	.config = &qcs615_aggre1_noc_regmap_config,

	.nodes = aggre1_noc_nodes,

	.num_nodes = ARRAY_SIZE(aggre1_noc_nodes),

	.bcms = aggre1_noc_bcms,

	.num_bcms = ARRAY_SIZE(aggre1_noc_bcms),

	.qos_requires_clocks = true,

};



static struct qcom_icc_bcm * const camnoc_virt_bcms[] = {
@@ -1289,7 +1491,16 @@ static struct qcom_icc_node * const config_noc_nodes[] = { 
	[SLAVE_SERVICE_CNOC] = &srvc_cnoc,

};



static const struct regmap_config qcs615_config_noc_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0x5080,

	.fast_io = true,

};



static const struct qcom_icc_desc qcs615_config_noc = {

	.config = &qcs615_config_noc_regmap_config,

	.nodes = config_noc_nodes,

	.num_nodes = ARRAY_SIZE(config_noc_nodes),

	.bcms = config_noc_bcms,
@@ -1302,7 +1513,16 @@ static struct qcom_icc_node * const dc_noc_nodes[] = { 
	[SLAVE_LLCC_CFG] = &qhs_llcc,

};



static const struct regmap_config qcs615_dc_noc_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0x3200,

	.fast_io = true,

};



static const struct qcom_icc_desc qcs615_dc_noc = {

	.config = &qcs615_dc_noc_regmap_config,

	.nodes = dc_noc_nodes,

	.num_nodes = ARRAY_SIZE(dc_noc_nodes),

};
@@ -1331,7 +1551,16 @@ static struct qcom_icc_node * const gem_noc_nodes[] = { 
	[SLAVE_SERVICE_GEM_NOC] = &srvc_gemnoc,

};



static const struct regmap_config qcs615_gem_noc_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0x3e200,

	.fast_io = true,

};



static const struct qcom_icc_desc qcs615_gem_noc = {

	.config = &qcs615_gem_noc_regmap_config,

	.nodes = gem_noc_nodes,

	.num_nodes = ARRAY_SIZE(gem_noc_nodes),

	.bcms = gem_noc_bcms,
@@ -1376,7 +1605,16 @@ static struct qcom_icc_node * const mmss_noc_nodes[] = { 
	[SLAVE_SERVICE_MNOC] = &srvc_mnoc,

};



static const struct regmap_config qcs615_mmss_noc_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0x1c100,

	.fast_io = true,

};



static const struct qcom_icc_desc qcs615_mmss_noc = {

	.config = &qcs615_mmss_noc_regmap_config,

	.nodes = mmss_noc_nodes,

	.num_nodes = ARRAY_SIZE(mmss_noc_nodes),

	.bcms = mmss_noc_bcms,
@@ -1418,7 +1656,16 @@ static struct qcom_icc_node * const system_noc_nodes[] = { 
	[SLAVE_TCU] = &xs_sys_tcu_cfg,

};



static const struct regmap_config qcs615_system_noc_regmap_config = {

	.reg_bits = 32,

	.reg_stride = 4,

	.val_bits = 32,

	.max_register = 0x1f300,

	.fast_io = true,

};



static const struct qcom_icc_desc qcs615_system_noc = {

	.config = &qcs615_system_noc_regmap_config,

	.nodes = system_noc_nodes,

	.num_nodes = ARRAY_SIZE(system_noc_nodes),

	.bcms = system_noc_bcms,