Unverified Commit 50cb86f2 authored by AlvinZhou's avatar AlvinZhou Committed by Tudor Ambarus
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spi: mxic: Add support for swapping byte 



Some SPI-NOR flash swap the bytes on a 16-bit boundary when
configured in Octal DTR mode. It means data format D0 D1 D2 D3
would be swapped to D1 D0 D3 D2. So that whether controller
support swapping bytes should be checked before enable Octal
DTR mode. Add swap byte support on a 16-bit boundary when
configured in Octal DTR mode for Macronix xSPI host controller
driver.

According dtr_swab in operation to enable/disable Macronix
xSPI host controller swap byte feature.

To make sure swap byte feature is working well, program data in
1S-1S-1S mode then read back and compare read data in 8D-8D-8D
mode.

This feature have been validated on byte-swap flash and
non-byte-swap flash.

Macronix xSPI host controller bit "HC_CFG_DATA_PASS" determine
the byte swap feature disabled/enabled and swap byte feature is
working on 8D-8D-8D mode only.

Suggested-by: default avatarMichael Walle <mwalle@kernel.org>
Signed-off-by: default avatarJaimeLiao <jaimeliao@mxic.com.tw>
Signed-off-by: default avatarAlvinZhou <alvinzhou@mxic.com.tw>
Acked-by: default avatarMark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20240926141956.2386374-6-alvinzhou.tw@gmail.com


Signed-off-by: default avatarTudor Ambarus <tudor.ambarus@linaro.org>
parent 030ace43

drivers/spi/spi-mxic.c

+13 −4
Original line number Diff line number Diff line
@@ -294,7 +294,8 @@ static void mxic_spi_hw_init(struct mxic_spi *mxic) 
	       mxic->regs + HC_CFG);

}



static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags)

static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags,

				bool swap16)

{

	int nio = 1;
@@ -305,6 +306,11 @@ static u32 mxic_spi_prep_hc_cfg(struct spi_device *spi, u32 flags) 
	else if (spi->mode & (SPI_TX_DUAL | SPI_RX_DUAL))

		nio = 2;



	if (swap16)

		flags &= ~HC_CFG_DATA_PASS;

	else

		flags |= HC_CFG_DATA_PASS;



	return flags | HC_CFG_NIO(nio) |

	       HC_CFG_TYPE(spi_get_chipselect(spi, 0), HC_CFG_TYPE_SPI_NOR) |

	       HC_CFG_SLV_ACT(spi_get_chipselect(spi, 0)) | HC_CFG_IDLE_SIO_LVL(1);
@@ -397,7 +403,8 @@ static ssize_t mxic_spi_mem_dirmap_read(struct spi_mem_dirmap_desc *desc, 
	if (WARN_ON(offs + desc->info.offset + len > U32_MAX))

		return -EINVAL;



	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);

	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),

	       mxic->regs + HC_CFG);



	writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),

	       mxic->regs + LRD_CFG);
@@ -441,7 +448,8 @@ static ssize_t mxic_spi_mem_dirmap_write(struct spi_mem_dirmap_desc *desc, 
	if (WARN_ON(offs + desc->info.offset + len > U32_MAX))

		return -EINVAL;



	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0), mxic->regs + HC_CFG);

	writel(mxic_spi_prep_hc_cfg(desc->mem->spi, 0, desc->info.op_tmpl.data.swap16),

	       mxic->regs + HC_CFG);



	writel(mxic_spi_mem_prep_op_cfg(&desc->info.op_tmpl, len),

	       mxic->regs + LWR_CFG);
@@ -518,7 +526,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem, 
	if (ret)

		return ret;



	writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN),

	writel(mxic_spi_prep_hc_cfg(mem->spi, HC_CFG_MAN_CS_EN, op->data.swap16),

	       mxic->regs + HC_CFG);



	writel(HC_EN_BIT, mxic->regs + HC_EN);
@@ -573,6 +581,7 @@ static const struct spi_controller_mem_ops mxic_spi_mem_ops = { 
static const struct spi_controller_mem_caps mxic_spi_mem_caps = {

	.dtr = true,

	.ecc = true,

	.swap16 = true,

};



static void mxic_spi_set_cs(struct spi_device *spi, bool lvl)